
Stephen Michael Gravini
Examiner (ID: 12967, Phone: (571)272-4875 , Office: P/3744 )
| Most Active Art Unit | 3753 |
| Art Unit(s) | 3749, 3753, 2162, 3743, 3404, 3744, 3622 |
| Total Applications | 3725 |
| Issued Applications | 2988 |
| Pending Applications | 212 |
| Abandoned Applications | 561 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17515669
[patent_doc_number] => 11294820
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-04-05
[patent_title] => Management of programming mode transitions to accommodate a constant size of data transfer between a host system and a memory sub-system
[patent_app_type] => utility
[patent_app_number] => 16/883826
[patent_app_country] => US
[patent_app_date] => 2020-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 11988
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16883826
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/883826 | Management of programming mode transitions to accommodate a constant size of data transfer between a host system and a memory sub-system | May 25, 2020 | Issued |
Array
(
[id] => 16299864
[patent_doc_number] => 20200285587
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-09-10
[patent_title] => Managing Availability Of Memory Pages
[patent_app_type] => utility
[patent_app_number] => 16/883561
[patent_app_country] => US
[patent_app_date] => 2020-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8070
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16883561
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/883561 | Managing availability of memory pages | May 25, 2020 | Issued |
Array
(
[id] => 16438972
[patent_doc_number] => 20200356298
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-11-12
[patent_title] => INFINITE MEMORY FABRIC HARDWARE IMPLEMENTATION WITH MEMORY
[patent_app_type] => utility
[patent_app_number] => 16/883701
[patent_app_country] => US
[patent_app_date] => 2020-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 33992
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 204
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16883701
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/883701 | Infinite memory fabric hardware implementation with memory | May 25, 2020 | Issued |
Array
(
[id] => 17352106
[patent_doc_number] => 11226742
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-01-18
[patent_title] => Semiconductor memory device including a control circuit and at least two memory cell arrays
[patent_app_type] => utility
[patent_app_number] => 16/883560
[patent_app_country] => US
[patent_app_date] => 2020-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 12823
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 250
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16883560
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/883560 | Semiconductor memory device including a control circuit and at least two memory cell arrays | May 25, 2020 | Issued |
Array
(
[id] => 17245630
[patent_doc_number] => 20210365374
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-11-25
[patent_title] => ALIASED MODE FOR CACHE CONTROLLER
[patent_app_type] => utility
[patent_app_number] => 16/882344
[patent_app_country] => US
[patent_app_date] => 2020-05-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17666
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16882344
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/882344 | Aliased mode for cache controller | May 21, 2020 | Issued |
Array
(
[id] => 17409036
[patent_doc_number] => 11249921
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-02-15
[patent_title] => Page modification encoding and caching
[patent_app_type] => utility
[patent_app_number] => 16/867793
[patent_app_country] => US
[patent_app_date] => 2020-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 14433
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16867793
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/867793 | Page modification encoding and caching | May 5, 2020 | Issued |
Array
(
[id] => 17824664
[patent_doc_number] => 11429612
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-08-30
[patent_title] => Address search circuit and method of semiconductor memory apparatus and controller therefor
[patent_app_type] => utility
[patent_app_number] => 16/841089
[patent_app_country] => US
[patent_app_date] => 2020-04-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 7020
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 238
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16841089
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/841089 | Address search circuit and method of semiconductor memory apparatus and controller therefor | Apr 5, 2020 | Issued |
Array
(
[id] => 16179098
[patent_doc_number] => 20200226066
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-07-16
[patent_title] => APPARATUS AND METHOD FOR EFFICIENT MANAGEMENT OF MULTI-LEVEL MEMORY
[patent_app_type] => utility
[patent_app_number] => 16/833337
[patent_app_country] => US
[patent_app_date] => 2020-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7417
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16833337
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/833337 | APPARATUS AND METHOD FOR EFFICIENT MANAGEMENT OF MULTI-LEVEL MEMORY | Mar 26, 2020 | Pending |
Array
(
[id] => 17269294
[patent_doc_number] => 11194721
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-12-07
[patent_title] => Invalidation and refresh of multi-tier distributed caches
[patent_app_type] => utility
[patent_app_number] => 16/821399
[patent_app_country] => US
[patent_app_date] => 2020-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 14
[patent_no_of_words] => 12637
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16821399
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/821399 | Invalidation and refresh of multi-tier distributed caches | Mar 16, 2020 | Issued |
Array
(
[id] => 17238422
[patent_doc_number] => 11182302
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-11-23
[patent_title] => Memory device, electronic device, and associated read method
[patent_app_type] => utility
[patent_app_number] => 16/820795
[patent_app_country] => US
[patent_app_date] => 2020-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 18
[patent_no_of_words] => 9226
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16820795
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/820795 | Memory device, electronic device, and associated read method | Mar 16, 2020 | Issued |
Array
(
[id] => 16271093
[patent_doc_number] => 20200272581
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-08-27
[patent_title] => METHOD FOR PROTECTING MEMORY AGAINST UNAUTHORIZED ACCESS
[patent_app_type] => utility
[patent_app_number] => 16/812660
[patent_app_country] => US
[patent_app_date] => 2020-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2788
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16812660
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/812660 | Method for protecting memory against unauthorized access | Mar 8, 2020 | Issued |
Array
(
[id] => 16160457
[patent_doc_number] => 20200218461
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-07-09
[patent_title] => Managing Data Reduction in Storage Systems Using Machine Learning
[patent_app_type] => utility
[patent_app_number] => 16/811173
[patent_app_country] => US
[patent_app_date] => 2020-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8063
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16811173
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/811173 | Managing data reduction in storage systems using machine learning | Mar 5, 2020 | Issued |
Array
(
[id] => 16271088
[patent_doc_number] => 20200272576
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-08-27
[patent_title] => Accelerating Access to Memory Banks in a Data Storage System
[patent_app_type] => utility
[patent_app_number] => 16/800913
[patent_app_country] => US
[patent_app_date] => 2020-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7599
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 239
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16800913
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/800913 | Accelerating access to memory banks in a data storage system | Feb 24, 2020 | Issued |
Array
(
[id] => 16192965
[patent_doc_number] => 20200233814
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-07-23
[patent_title] => PROGRAMMABLE ADDRESS RANGE ENGINE FOR LARGER REGION SIZES
[patent_app_type] => utility
[patent_app_number] => 16/786815
[patent_app_country] => US
[patent_app_date] => 2020-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 20144
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16786815
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/786815 | Programmable address range engine for larger region sizes | Feb 9, 2020 | Issued |
Array
(
[id] => 15966657
[patent_doc_number] => 20200167080
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-05-28
[patent_title] => SCALING-IN FOR GEOGRAPHICALLY DIVERSE STORAGE
[patent_app_type] => utility
[patent_app_number] => 16/779208
[patent_app_country] => US
[patent_app_date] => 2020-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12943
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 195
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16779208
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/779208 | Scaling-in for geographically diverse storage | Jan 30, 2020 | Issued |
Array
(
[id] => 17283140
[patent_doc_number] => 11200169
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-12-14
[patent_title] => Cache management for sequential IO operations
[patent_app_type] => utility
[patent_app_number] => 16/777129
[patent_app_country] => US
[patent_app_date] => 2020-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 16961
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 201
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16777129
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/777129 | Cache management for sequential IO operations | Jan 29, 2020 | Issued |
Array
(
[id] => 17252983
[patent_doc_number] => 11188472
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-11-30
[patent_title] => Caching streams of memory requests
[patent_app_type] => utility
[patent_app_number] => 16/774595
[patent_app_country] => US
[patent_app_date] => 2020-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 7144
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16774595
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/774595 | Caching streams of memory requests | Jan 27, 2020 | Issued |
Array
(
[id] => 16271082
[patent_doc_number] => 20200272570
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-08-27
[patent_title] => DATA STORAGE DEVICE AND CONTROL METHOD FOR NON-VOLATILE MEMORY
[patent_app_type] => utility
[patent_app_number] => 16/728294
[patent_app_country] => US
[patent_app_date] => 2019-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4056
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16728294
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/728294 | Data storage device and control method for non-volatile memory | Dec 26, 2019 | Issued |
Array
(
[id] => 15935657
[patent_doc_number] => 20200159462
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-05-21
[patent_title] => FAST INPUT/OUTPUT IN A CONTENT-ADDRESSABLE STORAGE ARCHITECTURE WITH PAGED METADATA
[patent_app_type] => utility
[patent_app_number] => 16/728599
[patent_app_country] => US
[patent_app_date] => 2019-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7981
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 226
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16728599
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/728599 | Fast input/output in a content-addressable storage architecture with paged metadata | Dec 26, 2019 | Issued |
Array
(
[id] => 18204148
[patent_doc_number] => 11586539
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-02-21
[patent_title] => Adaptive cache management based on programming model information
[patent_app_type] => utility
[patent_app_number] => 16/713940
[patent_app_country] => US
[patent_app_date] => 2019-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 7220
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16713940
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/713940 | Adaptive cache management based on programming model information | Dec 12, 2019 | Issued |