Search

Stephen T. Gordon

Examiner (ID: 18308, Phone: (571)272-6661 , Office: P/3612 )

Most Active Art Unit
3612
Art Unit(s)
3612, 3616, 3614, 2899, 3642, 3107
Total Applications
2786
Issued Applications
2310
Pending Applications
130
Abandoned Applications
374

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17840791 [patent_doc_number] => 20220278097 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-01 [patent_title] => Semiconductor Device and Method of Forming Same [patent_app_type] => utility [patent_app_number] => 17/186293 [patent_app_country] => US [patent_app_date] => 2021-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10293 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17186293 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/186293
Semiconductor device and method of forming same Feb 25, 2021 Issued
Array ( [id] => 17758185 [patent_doc_number] => 11398484 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-07-26 [patent_title] => Semiconductor device with air gap between bit line and capacitor contact and method for forming the same [patent_app_type] => utility [patent_app_number] => 17/178984 [patent_app_country] => US [patent_app_date] => 2021-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6984 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17178984 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/178984
Semiconductor device with air gap between bit line and capacitor contact and method for forming the same Feb 17, 2021 Issued
Array ( [id] => 16888924 [patent_doc_number] => 20210175121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => THROUGH ELECTRODE SUBSTRATE, METHOD OF MANUFACTURING THROUGH ELECTRODE SUBSTRATE, AND MOUNTING SUBSTRATE [patent_app_type] => utility [patent_app_number] => 17/178659 [patent_app_country] => US [patent_app_date] => 2021-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16537 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17178659 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/178659
Through electrode substrate, method of manufacturing through electrode substrate, and mounting substrate Feb 17, 2021 Issued
Array ( [id] => 16904902 [patent_doc_number] => 20210183818 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => SEMICONDUCTOR PACKAGE HAVING CHIP STACK [patent_app_type] => utility [patent_app_number] => 17/169701 [patent_app_country] => US [patent_app_date] => 2021-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7629 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17169701 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/169701
Semiconductor package having chip stack Feb 7, 2021 Issued
Array ( [id] => 17417140 [patent_doc_number] => 20220052044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => Epitaxy Regions Extending Below STI Regions and Profiles Thereof [patent_app_type] => utility [patent_app_number] => 17/167336 [patent_app_country] => US [patent_app_date] => 2021-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8581 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17167336 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/167336
Epitaxy regions extending below STI regions and profiles thereof Feb 3, 2021 Issued
Array ( [id] => 17188788 [patent_doc_number] => 20210335673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => INTERCONNECT STRUCTURES FOR SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/166548 [patent_app_country] => US [patent_app_date] => 2021-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11026 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17166548 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/166548
Interconnect structures for semiconductor devices and methods of manufacturing the same Feb 2, 2021 Issued
Array ( [id] => 17925966 [patent_doc_number] => 11469229 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-11 [patent_title] => Semiconductor device and method [patent_app_type] => utility [patent_app_number] => 17/149950 [patent_app_country] => US [patent_app_date] => 2021-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 30 [patent_no_of_words] => 11892 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17149950 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/149950
Semiconductor device and method Jan 14, 2021 Issued
Array ( [id] => 17737971 [patent_doc_number] => 20220223433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => WAFER-TO-WAFER INTERCONNECTION STRUCTURE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/146438 [patent_app_country] => US [patent_app_date] => 2021-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3313 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17146438 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/146438
Wafer-to-wafer interconnection structure and method of manufacturing the same Jan 10, 2021 Issued
Array ( [id] => 18371923 [patent_doc_number] => 11652105 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-16 [patent_title] => Epitaxy regions with large landing areas for contact plugs [patent_app_type] => utility [patent_app_number] => 17/143681 [patent_app_country] => US [patent_app_date] => 2021-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 8266 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17143681 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/143681
Epitaxy regions with large landing areas for contact plugs Jan 6, 2021 Issued
Array ( [id] => 17908749 [patent_doc_number] => 11462612 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-04 [patent_title] => Semiconductor device structure [patent_app_type] => utility [patent_app_number] => 17/142970 [patent_app_country] => US [patent_app_date] => 2021-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 9464 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17142970 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/142970
Semiconductor device structure Jan 5, 2021 Issued
Array ( [id] => 16873824 [patent_doc_number] => 20210167291 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => Vapor Jet Printing [patent_app_type] => utility [patent_app_number] => 17/142490 [patent_app_country] => US [patent_app_date] => 2021-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13148 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17142490 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/142490
Vapor jet printing Jan 5, 2021 Issued
Array ( [id] => 18464338 [patent_doc_number] => 11688632 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-27 [patent_title] => Semiconductor device with linerless contacts [patent_app_type] => utility [patent_app_number] => 17/136595 [patent_app_country] => US [patent_app_date] => 2020-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6595 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17136595 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/136595
Semiconductor device with linerless contacts Dec 28, 2020 Issued
Array ( [id] => 17956455 [patent_doc_number] => 11482570 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-25 [patent_title] => Methods of forming magnetoresistive devices and integrated circuits [patent_app_type] => utility [patent_app_number] => 17/134865 [patent_app_country] => US [patent_app_date] => 2020-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6169 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17134865 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/134865
Methods of forming magnetoresistive devices and integrated circuits Dec 27, 2020 Issued
Array ( [id] => 16850696 [patent_doc_number] => 20210151441 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => METHOD FOR PREPARING SEMICONDUCTOR DEVICE WITH AIR GAP STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/130478 [patent_app_country] => US [patent_app_date] => 2020-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6624 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17130478 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/130478
Method for preparing semiconductor device with air gap structure Dec 21, 2020 Issued
Array ( [id] => 17956490 [patent_doc_number] => 11482605 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-25 [patent_title] => Work function metal gate device [patent_app_type] => utility [patent_app_number] => 17/128168 [patent_app_country] => US [patent_app_date] => 2020-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4002 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17128168 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/128168
Work function metal gate device Dec 19, 2020 Issued
Array ( [id] => 17862834 [patent_doc_number] => 11443995 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-13 [patent_title] => Integrated circuit package and method [patent_app_type] => utility [patent_app_number] => 17/120859 [patent_app_country] => US [patent_app_date] => 2020-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 48 [patent_no_of_words] => 12669 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17120859 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/120859
Integrated circuit package and method Dec 13, 2020 Issued
Array ( [id] => 16812390 [patent_doc_number] => 20210134945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => ISOLATION STRUCTURES OF SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 17/120852 [patent_app_country] => US [patent_app_date] => 2020-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13895 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17120852 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/120852
Isolation structures of semiconductor devices Dec 13, 2020 Issued
Array ( [id] => 17590768 [patent_doc_number] => 11329045 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-10 [patent_title] => Field effect transistor, method for making the same and layout in process of forming the same [patent_app_type] => utility [patent_app_number] => 17/118428 [patent_app_country] => US [patent_app_date] => 2020-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 7602 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17118428 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/118428
Field effect transistor, method for making the same and layout in process of forming the same Dec 9, 2020 Issued
Array ( [id] => 16781716 [patent_doc_number] => 20210118795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 17/116926 [patent_app_country] => US [patent_app_date] => 2020-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5739 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17116926 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/116926
Semiconductor structure and method of forming semiconductor package Dec 8, 2020 Issued
Array ( [id] => 16781666 [patent_doc_number] => 20210118745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/114347 [patent_app_country] => US [patent_app_date] => 2020-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19562 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17114347 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/114347
Method of manufacturing a semiconductor device and a semiconductor device Dec 6, 2020 Issued
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