Search

Stephen T. Gordon

Examiner (ID: 147, Phone: (571)272-6661 , Office: P/3612 )

Most Active Art Unit
3612
Art Unit(s)
3612, 3642, 3616, 3614, 3107, 2899
Total Applications
2791
Issued Applications
2320
Pending Applications
117
Abandoned Applications
376

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16835156 [patent_doc_number] => 11011415 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-18 [patent_title] => Airgap vias in electrical interconnects [patent_app_type] => utility [patent_app_number] => 16/858484 [patent_app_country] => US [patent_app_date] => 2020-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 5632 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 405 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16858484 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/858484
Airgap vias in electrical interconnects Apr 23, 2020 Issued
Array ( [id] => 19952758 [patent_doc_number] => 12324143 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-03 [patent_title] => Methods of utilizing etch-stop material during fabrication of capacitors, integrated assemblies comprising capacitors [patent_app_type] => utility [patent_app_number] => 16/851588 [patent_app_country] => US [patent_app_date] => 2020-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 1052 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16851588 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/851588
Methods of utilizing etch-stop material during fabrication of capacitors, integrated assemblies comprising capacitors Apr 16, 2020 Issued
Array ( [id] => 16210669 [patent_doc_number] => 20200243659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => TRANSISTORS WITH DUAL GATE CONDUCTORS, AND ASSOCIATED METHODS [patent_app_type] => utility [patent_app_number] => 16/846941 [patent_app_country] => US [patent_app_date] => 2020-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9854 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16846941 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/846941
TRANSISTORS WITH DUAL GATE CONDUCTORS, AND ASSOCIATED METHODS Apr 12, 2020 Abandoned
Array ( [id] => 16881313 [patent_doc_number] => 11031471 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-08 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 16/846434 [patent_app_country] => US [patent_app_date] => 2020-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 43 [patent_no_of_words] => 17052 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16846434 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/846434
Semiconductor device Apr 12, 2020 Issued
Array ( [id] => 16850711 [patent_doc_number] => 20210151456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/847251 [patent_app_country] => US [patent_app_date] => 2020-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6879 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16847251 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/847251
Semiconductor device and manufacturing method of semiconductor device Apr 12, 2020 Issued
Array ( [id] => 16692284 [patent_doc_number] => 20210074763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => NONVOLATILE MEMORY DEVICE HAVING RESISTANCE CHANGE MEMORY LAYER [patent_app_type] => utility [patent_app_number] => 16/844806 [patent_app_country] => US [patent_app_date] => 2020-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9734 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16844806 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/844806
Nonvolatile memory device having resistance change memory layer Apr 8, 2020 Issued
Array ( [id] => 17332422 [patent_doc_number] => 11222890 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-11 [patent_title] => Integrated power semiconductor device and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/839089 [patent_app_country] => US [patent_app_date] => 2020-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 49 [patent_no_of_words] => 24763 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 1360 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16839089 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/839089
Integrated power semiconductor device and method for manufacturing the same Apr 2, 2020 Issued
Array ( [id] => 17700368 [patent_doc_number] => 11374103 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-28 [patent_title] => Gate structure and photomask of NAND memory and method for making the same [patent_app_type] => utility [patent_app_number] => 16/837961 [patent_app_country] => US [patent_app_date] => 2020-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 19 [patent_no_of_words] => 4763 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16837961 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/837961
Gate structure and photomask of NAND memory and method for making the same Mar 31, 2020 Issued
Array ( [id] => 16348223 [patent_doc_number] => 20200312874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => 3D-NAND MOLD [patent_app_type] => utility [patent_app_number] => 16/833899 [patent_app_country] => US [patent_app_date] => 2020-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7127 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16833899 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/833899
3D-NAND mold Mar 29, 2020 Issued
Array ( [id] => 16660782 [patent_doc_number] => 20210057419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/833919 [patent_app_country] => US [patent_app_date] => 2020-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8424 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16833919 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/833919
Semiconductor memory device Mar 29, 2020 Issued
Array ( [id] => 19031298 [patent_doc_number] => 11930674 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-12 [patent_title] => Display substrate and preparation method thereof, and display apparatus [patent_app_type] => utility [patent_app_number] => 17/261034 [patent_app_country] => US [patent_app_date] => 2020-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 14423 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17261034 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/261034
Display substrate and preparation method thereof, and display apparatus Mar 26, 2020 Issued
Array ( [id] => 16180600 [patent_doc_number] => 20200227569 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/831958 [patent_app_country] => US [patent_app_date] => 2020-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4867 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16831958 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/831958
Semiconductor device Mar 26, 2020 Issued
Array ( [id] => 18804510 [patent_doc_number] => 11837676 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-05 [patent_title] => Optical semiconductor device and optical transmission apparatus [patent_app_type] => utility [patent_app_number] => 16/832713 [patent_app_country] => US [patent_app_date] => 2020-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 45 [patent_no_of_words] => 8498 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16832713 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/832713
Optical semiconductor device and optical transmission apparatus Mar 26, 2020 Issued
Array ( [id] => 16348185 [patent_doc_number] => 20200312836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/828958 [patent_app_country] => US [patent_app_date] => 2020-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5686 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16828958 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/828958
Semiconductor device and method of fabricating the same Mar 24, 2020 Issued
Array ( [id] => 16180442 [patent_doc_number] => 20200227411 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => TRANSISTOR AND LOGIC GATE [patent_app_type] => utility [patent_app_number] => 16/828939 [patent_app_country] => US [patent_app_date] => 2020-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13487 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16828939 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/828939
Transistor and logic gate Mar 23, 2020 Issued
Array ( [id] => 16846047 [patent_doc_number] => 11018143 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-05-25 [patent_title] => Antifuse OTP structures with hybrid low-voltage devices [patent_app_type] => utility [patent_app_number] => 16/816537 [patent_app_country] => US [patent_app_date] => 2020-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7314 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16816537 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/816537
Antifuse OTP structures with hybrid low-voltage devices Mar 11, 2020 Issued
Array ( [id] => 16348315 [patent_doc_number] => 20200312966 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => SILICON CARBIDE EPITAXIAL SUBSTRATE, METHOD OF MANUFACTURING THEREOF, SILICON CARBIDE SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THEREOF [patent_app_type] => utility [patent_app_number] => 16/814554 [patent_app_country] => US [patent_app_date] => 2020-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5555 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16814554 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/814554
Silicon carbide epitaxial substrate, method of manufacturing thereof, silicon carbide semiconductor device, and method of manufacturing thereof Mar 9, 2020 Issued
Array ( [id] => 17085773 [patent_doc_number] => 20210280780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => DIFFUSION BARRIER LAYER IN PROGRAMMABLE METALLIZATION CELL [patent_app_type] => utility [patent_app_number] => 16/807600 [patent_app_country] => US [patent_app_date] => 2020-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7169 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16807600 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/807600
Diffusion barrier layer in programmable metallization cell Mar 2, 2020 Issued
Array ( [id] => 17862868 [patent_doc_number] => 11444029 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-13 [patent_title] => Back-end-of-line interconnect structures with varying aspect ratios [patent_app_type] => utility [patent_app_number] => 16/799048 [patent_app_country] => US [patent_app_date] => 2020-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5477 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 326 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16799048 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/799048
Back-end-of-line interconnect structures with varying aspect ratios Feb 23, 2020 Issued
Array ( [id] => 18205469 [patent_doc_number] => 11587874 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-21 [patent_title] => Resistance reduction for word lines in memory arrays [patent_app_type] => utility [patent_app_number] => 16/799448 [patent_app_country] => US [patent_app_date] => 2020-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 6681 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16799448 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/799448
Resistance reduction for word lines in memory arrays Feb 23, 2020 Issued
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