Search

Stephen T. Gordon

Examiner (ID: 147, Phone: (571)272-6661 , Office: P/3612 )

Most Active Art Unit
3612
Art Unit(s)
3612, 3642, 3616, 3614, 3107, 2899
Total Applications
2791
Issued Applications
2320
Pending Applications
117
Abandoned Applications
376

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16593921 [patent_doc_number] => 10903198 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-26 [patent_title] => Semiconductor package assembly and method for forming the same [patent_app_type] => utility [patent_app_number] => 16/674298 [patent_app_country] => US [patent_app_date] => 2019-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 6543 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16674298 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/674298
Semiconductor package assembly and method for forming the same Nov 4, 2019 Issued
Array ( [id] => 16812195 [patent_doc_number] => 20210134750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => CONDUCTIVE MEMBERS FOR DIE ATTACH IN FLIP CHIP PACKAGES [patent_app_type] => utility [patent_app_number] => 16/669070 [patent_app_country] => US [patent_app_date] => 2019-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4435 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16669070 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/669070
Conductive members for die attach in flip chip packages Oct 29, 2019 Issued
Array ( [id] => 16536622 [patent_doc_number] => 10879236 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => Bootstrap metal-oxide-semiconductor (MOS) device integrated with a high voltage MOS (HVMOS) device and a high voltage junction termination (HVJT) device [patent_app_type] => utility [patent_app_number] => 16/662496 [patent_app_country] => US [patent_app_date] => 2019-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 29 [patent_no_of_words] => 19789 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16662496 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/662496
Bootstrap metal-oxide-semiconductor (MOS) device integrated with a high voltage MOS (HVMOS) device and a high voltage junction termination (HVJT) device Oct 23, 2019 Issued
Array ( [id] => 15503779 [patent_doc_number] => 20200052078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => LOW COLLECTOR CONTACT RESISTANCE HETEROJUNCTION BIPOLAR TRANSISTORS [patent_app_type] => utility [patent_app_number] => 16/660006 [patent_app_country] => US [patent_app_date] => 2019-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4215 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16660006 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/660006
LOW COLLECTOR CONTACT RESISTANCE HETEROJUNCTION BIPOLAR TRANSISTORS Oct 21, 2019 Abandoned
Array ( [id] => 16464106 [patent_doc_number] => 10847467 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-24 [patent_title] => Power-delivery methods for embedded multi-die interconnect bridges and methods of assembling same [patent_app_type] => utility [patent_app_number] => 16/658866 [patent_app_country] => US [patent_app_date] => 2019-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 8346 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16658866 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/658866
Power-delivery methods for embedded multi-die interconnect bridges and methods of assembling same Oct 20, 2019 Issued
Array ( [id] => 16653520 [patent_doc_number] => 10930713 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Display panel and display apparatus having the same [patent_app_type] => utility [patent_app_number] => 16/599436 [patent_app_country] => US [patent_app_date] => 2019-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 12767 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16599436 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/599436
Display panel and display apparatus having the same Oct 10, 2019 Issued
Array ( [id] => 16765681 [patent_doc_number] => 20210111263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => OHMIC ALLOY CONTACT REGION SEALING LAYER [patent_app_type] => utility [patent_app_number] => 16/599650 [patent_app_country] => US [patent_app_date] => 2019-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2904 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -31 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16599650 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/599650
Ohmic alloy contact region sealing layer Oct 10, 2019 Issued
Array ( [id] => 17224744 [patent_doc_number] => 11177254 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-16 [patent_title] => Stacked transistor device [patent_app_type] => utility [patent_app_number] => 16/599360 [patent_app_country] => US [patent_app_date] => 2019-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 25 [patent_no_of_words] => 7743 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16599360 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/599360
Stacked transistor device Oct 10, 2019 Issued
Array ( [id] => 16773921 [patent_doc_number] => 10985042 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-20 [patent_title] => SiC substrate, SiC epitaxial wafer, and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/599645 [patent_app_country] => US [patent_app_date] => 2019-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 4330 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16599645 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/599645
SiC substrate, SiC epitaxial wafer, and method of manufacturing the same Oct 10, 2019 Issued
Array ( [id] => 15905965 [patent_doc_number] => 20200152503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => INTEGRATED ELECTRONIC CIRCUIT WITH AIRGAPS [patent_app_type] => utility [patent_app_number] => 16/577332 [patent_app_country] => US [patent_app_date] => 2019-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6073 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16577332 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/577332
Integrated electronic circuit with airgaps Sep 19, 2019 Issued
Array ( [id] => 15351561 [patent_doc_number] => 20200013672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-09 [patent_title] => CAP STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/573209 [patent_app_country] => US [patent_app_date] => 2019-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2904 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16573209 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/573209
Cap structure Sep 16, 2019 Issued
Array ( [id] => 15331655 [patent_doc_number] => 20200006157 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => Method for Patterning a Lanthanum Containing Layer [patent_app_type] => utility [patent_app_number] => 16/569820 [patent_app_country] => US [patent_app_date] => 2019-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5944 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16569820 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/569820
Method for patterning a lanthanum containing layer Sep 12, 2019 Issued
Array ( [id] => 18857511 [patent_doc_number] => 11855108 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Solid-state imaging element and electronic device [patent_app_type] => utility [patent_app_number] => 17/250708 [patent_app_country] => US [patent_app_date] => 2019-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 5658 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17250708 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/250708
Solid-state imaging element and electronic device Sep 1, 2019 Issued
Array ( [id] => 16699926 [patent_doc_number] => 10950534 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-16 [patent_title] => Through-substrate via structure and method of manufacture [patent_app_type] => utility [patent_app_number] => 16/545139 [patent_app_country] => US [patent_app_date] => 2019-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6253 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16545139 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/545139
Through-substrate via structure and method of manufacture Aug 19, 2019 Issued
Array ( [id] => 16586432 [patent_doc_number] => 20210020834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => MEMORY DEVICE AND A METHOD FOR FORMING THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/513745 [patent_app_country] => US [patent_app_date] => 2019-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7330 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16513745 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/513745
Memory device and a method for forming the memory device Jul 16, 2019 Issued
Array ( [id] => 16210615 [patent_doc_number] => 20200243605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING A DATA STORAGE PATTERN AND A METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/513925 [patent_app_country] => US [patent_app_date] => 2019-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8434 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16513925 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/513925
Semiconductor device including a data storage pattern and a method of manufacturing the same Jul 16, 2019 Issued
Array ( [id] => 16448457 [patent_doc_number] => 10840388 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-11-17 [patent_title] => Varactor with hyper-abrupt junction region including a superlattice [patent_app_type] => utility [patent_app_number] => 16/513932 [patent_app_country] => US [patent_app_date] => 2019-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 5770 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16513932 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/513932
Varactor with hyper-abrupt junction region including a superlattice Jul 16, 2019 Issued
Array ( [id] => 17590827 [patent_doc_number] => 11329104 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-10 [patent_title] => Display panel and display device [patent_app_type] => utility [patent_app_number] => 16/496630 [patent_app_country] => US [patent_app_date] => 2019-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3306 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16496630 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/496630
Display panel and display device Jul 11, 2019 Issued
Array ( [id] => 18175193 [patent_doc_number] => 11574910 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-07 [patent_title] => Device with air-gaps to reduce coupling capacitance and process for forming such [patent_app_type] => utility [patent_app_number] => 16/457677 [patent_app_country] => US [patent_app_date] => 2019-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6943 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16457677 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/457677
Device with air-gaps to reduce coupling capacitance and process for forming such Jun 27, 2019 Issued
Array ( [id] => 14938631 [patent_doc_number] => 20190304954 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => 3D IC PACKAGE WITH RDL INTERPOSER AND RELATED METHOD [patent_app_type] => utility [patent_app_number] => 16/447335 [patent_app_country] => US [patent_app_date] => 2019-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5975 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16447335 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/447335
3D IC package with RDL interposer and related method Jun 19, 2019 Issued
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