Stephen T. Gordon

Array ( [id] => 13996593 [patent_doc_number] => 20190067454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => FinFET Device and Method of Forming Same [patent_app_type] => utility [patent_app_number] => 15/829705 [patent_app_country] => US [patent_app_date] => 2017-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11339 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15829705 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14672045 [patent_doc_number] => 10373942 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-06 [patent_title] => Logic layout with reduced area and method of making the same [patent_app_type] => utility [patent_app_number] => 15/829459 [patent_app_country] => US [patent_app_date] => 2017-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 64 [patent_no_of_words] => 4274 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15829459 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16781833 [patent_doc_number] => 20210118912 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => SEMICONDUCTOR PATTERNING [patent_app_type] => utility [patent_app_number] => 16/463670 [patent_app_country] => US [patent_app_date] => 2017-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2340 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16463670 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12243409 [patent_doc_number] => 20180076272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-15 [patent_title] => 'ELECTRO-OPTICAL DEVICE AND ELECTRONIC APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/815295 [patent_app_country] => US [patent_app_date] => 2017-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 27129 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15815295 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16148115 [patent_doc_number] => 10707134 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-07 [patent_title] => Fin field-effect transistor and fabrication method thereof [patent_app_type] => utility [patent_app_number] => 15/810398 [patent_app_country] => US [patent_app_date] => 2017-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 8389 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15810398 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16148115 [patent_doc_number] => 10707134 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-07 [patent_title] => Fin field-effect transistor and fabrication method thereof [patent_app_type] => utility [patent_app_number] => 15/810398 [patent_app_country] => US [patent_app_date] => 2017-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 8389 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15810398 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12738820 [patent_doc_number] => 20180138107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-17 [patent_title] => LEAD FRAME AND ELECTRONIC COMPONENT DEVICE [patent_app_type] => utility [patent_app_number] => 15/810261 [patent_app_country] => US [patent_app_date] => 2017-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12033 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15810261 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13145785 [patent_doc_number] => 10090232 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-10-02 [patent_title] => Bumpless fan-out chip stacking structure and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 15/810256 [patent_app_country] => US [patent_app_date] => 2017-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4922 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15810256 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15315695 [patent_doc_number] => 10522564 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Ferroelectric memory device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/810177 [patent_app_country] => US [patent_app_date] => 2017-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6075 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15810177 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13145827 [patent_doc_number] => 10090253 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-02 [patent_title] => Semiconductor package [patent_app_type] => utility [patent_app_number] => 15/811067 [patent_app_country] => US [patent_app_date] => 2017-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 23 [patent_no_of_words] => 7927 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15811067 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12779203 [patent_doc_number] => 20180151569 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-31 [patent_title] => Integrated Circuit Having a Vertical Power MOS Transistor [patent_app_type] => utility [patent_app_number] => 15/801724 [patent_app_country] => US [patent_app_date] => 2017-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5598 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15801724 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12188768 [patent_doc_number] => 20180047704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'MULTI-CHIP PACKAGE WITH INTERCONNECTS EXTENDING THROUGH LOGIC CHIP' [patent_app_type] => utility [patent_app_number] => 15/799036 [patent_app_country] => US [patent_app_date] => 2017-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5962 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15799036 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15984807 [patent_doc_number] => 10672742 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => Semiconductor device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 15/794286 [patent_app_country] => US [patent_app_date] => 2017-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 57 [patent_no_of_words] => 6517 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15794286 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13862039 [patent_doc_number] => 10192744 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-29 [patent_title] => Semiconductor device, related manufacturing method, and related electronic device [patent_app_type] => utility [patent_app_number] => 15/728395 [patent_app_country] => US [patent_app_date] => 2017-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5182 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15728395 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12650721 [patent_doc_number] => 20180108738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-19 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/719597 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17034 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15719597 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16120165 [patent_doc_number] => 20200212105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => ASYMMETRIC SELECTOR ELEMENT FOR LOW VOLTAGE BIPOLAR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 16/634109 [patent_app_country] => US [patent_app_date] => 2017-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10141 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16634109 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16566957 [patent_doc_number] => 10892334 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-12 [patent_title] => n-Type SiC single crystal substrate, method for producing same and SiC epitaxial wafer [patent_app_type] => utility [patent_app_number] => 16/333269 [patent_app_country] => US [patent_app_date] => 2017-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 7870 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16333269 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14453957 [patent_doc_number] => 10322930 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Semiconductor arrangement and formation thereof [patent_app_type] => utility [patent_app_number] => 15/706916 [patent_app_country] => US [patent_app_date] => 2017-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 4601 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15706916 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14094109 [patent_doc_number] => 10242968 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-26 [patent_title] => Interconnect structure and semiconductor structures for assembly of cryogenic electronic packages [patent_app_type] => utility [patent_app_number] => 15/684393 [patent_app_country] => US [patent_app_date] => 2017-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 45 [patent_no_of_words] => 63624 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 329 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15684393 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13957549 [patent_doc_number] => 20190055118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-21 [patent_title] => MEMS DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 15/680056 [patent_app_country] => US [patent_app_date] => 2017-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6132 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15680056 [rel_patent_id] =>[rel_patent_doc_number] =>)