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Stephen W Jordan

Examiner (ID: 9960)

Most Active Art Unit
1725
Art Unit(s)
1725
Total Applications
1
Issued Applications
0
Pending Applications
0
Abandoned Applications
1

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1192872 [patent_doc_number] => 06730523 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-04 [patent_title] => 'Low temperature chemical vapor deposition process for forming bismuth-containing ceramic thin films useful in ferroelectric memory devices' [patent_app_type] => B2 [patent_app_number] => 09/873138 [patent_app_country] => US [patent_app_date] => 2001-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 9304 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/730/06730523.pdf [firstpage_image] =>[orig_patent_app_number] => 09873138 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/873138
Low temperature chemical vapor deposition process for forming bismuth-containing ceramic thin films useful in ferroelectric memory devices May 31, 2001 Issued
Array ( [id] => 6898585 [patent_doc_number] => 20010046750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-29 [patent_title] => 'Method for manufacturing semiconductor device having a STI structure' [patent_app_type] => new [patent_app_number] => 09/862517 [patent_app_country] => US [patent_app_date] => 2001-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3582 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20010046750.pdf [firstpage_image] =>[orig_patent_app_number] => 09862517 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/862517
Method for manufacturing semiconductor device having a STI structure May 22, 2001 Abandoned
Array ( [id] => 6562909 [patent_doc_number] => 20020164836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-07 [patent_title] => 'Method of manufacturing printed circuit board' [patent_app_type] => new [patent_app_number] => 09/849247 [patent_app_country] => US [patent_app_date] => 2001-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2613 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20020164836.pdf [firstpage_image] =>[orig_patent_app_number] => 09849247 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/849247
Method of manufacturing printed circuit board May 6, 2001 Abandoned
Array ( [id] => 6563502 [patent_doc_number] => 20020164875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-07 [patent_title] => 'Thermal mechanical planarization in integrated circuits' [patent_app_type] => new [patent_app_number] => 09/848997 [patent_app_country] => US [patent_app_date] => 2001-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2057 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20020164875.pdf [firstpage_image] =>[orig_patent_app_number] => 09848997 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/848997
Thermal mechanical planarization in integrated circuits May 3, 2001 Abandoned
Array ( [id] => 6563392 [patent_doc_number] => 20020164868 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-07 [patent_title] => 'Method for forming a silicon dioxide-low k dielectric stack' [patent_app_type] => new [patent_app_number] => 09/847087 [patent_app_country] => US [patent_app_date] => 2001-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1900 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20020164868.pdf [firstpage_image] =>[orig_patent_app_number] => 09847087 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/847087
Method for forming a silicon dioxide-low k dielectric stack May 1, 2001 Abandoned
Array ( [id] => 6563710 [patent_doc_number] => 20020164889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-07 [patent_title] => 'Method for improving adhesion of low k materials with adjacent layer' [patent_app_type] => new [patent_app_number] => 09/847107 [patent_app_country] => US [patent_app_date] => 2001-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2208 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20020164889.pdf [firstpage_image] =>[orig_patent_app_number] => 09847107 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/847107
Method for improving adhesion of low k materials with adjacent layer May 1, 2001 Abandoned
Array ( [id] => 6892093 [patent_doc_number] => 20010018255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-30 [patent_title] => 'MOS transistor for high-speed and high-performance operation and manufacturing method thereof' [patent_app_type] => new [patent_app_number] => 09/847639 [patent_app_country] => US [patent_app_date] => 2001-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3044 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20010018255.pdf [firstpage_image] =>[orig_patent_app_number] => 09847639 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/847639
MOS transistor for high-speed and high-performance operation and manufacturing method thereof May 1, 2001 Issued
Array ( [id] => 1134445 [patent_doc_number] => 06784098 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-31 [patent_title] => 'Method for forming salicide process' [patent_app_type] => B1 [patent_app_number] => 09/845477 [patent_app_country] => US [patent_app_date] => 2001-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 6441 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 465 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/784/06784098.pdf [firstpage_image] =>[orig_patent_app_number] => 09845477 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/845477
Method for forming salicide process Apr 29, 2001 Issued
Array ( [id] => 1409991 [patent_doc_number] => 06528412 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Depositing an adhesion skin layer and a conformal seed layer to fill an interconnect opening' [patent_app_type] => B1 [patent_app_number] => 09/844727 [patent_app_country] => US [patent_app_date] => 2001-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 23 [patent_no_of_words] => 6236 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/528/06528412.pdf [firstpage_image] =>[orig_patent_app_number] => 09844727 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/844727
Depositing an adhesion skin layer and a conformal seed layer to fill an interconnect opening Apr 29, 2001 Issued
Array ( [id] => 1418353 [patent_doc_number] => 06514843 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-04 [patent_title] => 'Method of enhanced oxidation of MOS transistor gate corners' [patent_app_type] => B2 [patent_app_number] => 09/844977 [patent_app_country] => US [patent_app_date] => 2001-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3169 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/514/06514843.pdf [firstpage_image] =>[orig_patent_app_number] => 09844977 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/844977
Method of enhanced oxidation of MOS transistor gate corners Apr 26, 2001 Issued
Array ( [id] => 6986900 [patent_doc_number] => 20010036732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-01 [patent_title] => 'Method of manufacturing semiconductor device having minute gate electrodes' [patent_app_type] => new [patent_app_number] => 09/841347 [patent_app_country] => US [patent_app_date] => 2001-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10488 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20010036732.pdf [firstpage_image] =>[orig_patent_app_number] => 09841347 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/841347
Method of manufacturing semiconductor device having minute gate electrodes Apr 23, 2001 Abandoned
Array ( [id] => 544199 [patent_doc_number] => 07163892 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-16 [patent_title] => 'Process for producing integrated circuit, and substrate with integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/275087 [patent_app_country] => US [patent_app_date] => 2001-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 9947 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/163/07163892.pdf [firstpage_image] =>[orig_patent_app_number] => 10275087 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/275087
Process for producing integrated circuit, and substrate with integrated circuit Apr 22, 2001 Issued
Array ( [id] => 6594932 [patent_doc_number] => 20020042165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-11 [patent_title] => 'Process for producing oxide thin films' [patent_app_type] => new [patent_app_number] => 09/835737 [patent_app_country] => US [patent_app_date] => 2001-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6677 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20020042165.pdf [firstpage_image] =>[orig_patent_app_number] => 09835737 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/835737
Process for producing oxide thin films Apr 15, 2001 Issued
Array ( [id] => 1517390 [patent_doc_number] => 06500766 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-31 [patent_title] => 'Post-cleaning method of a via etching process' [patent_app_type] => B2 [patent_app_number] => 09/832267 [patent_app_country] => US [patent_app_date] => 2001-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1568 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/500/06500766.pdf [firstpage_image] =>[orig_patent_app_number] => 09832267 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/832267
Post-cleaning method of a via etching process Apr 10, 2001 Issued
Array ( [id] => 1354677 [patent_doc_number] => 06576535 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-10 [patent_title] => 'Carbon doped epitaxial layer for high speed CB-CMOS' [patent_app_type] => B2 [patent_app_number] => 09/829897 [patent_app_country] => US [patent_app_date] => 2001-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3686 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/576/06576535.pdf [firstpage_image] =>[orig_patent_app_number] => 09829897 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/829897
Carbon doped epitaxial layer for high speed CB-CMOS Apr 10, 2001 Issued
Array ( [id] => 7028167 [patent_doc_number] => 20010014509 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-16 [patent_title] => 'Method and structure for a semiconductor fuse' [patent_app_type] => new [patent_app_number] => 09/827871 [patent_app_country] => US [patent_app_date] => 2001-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3326 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20010014509.pdf [firstpage_image] =>[orig_patent_app_number] => 09827871 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/827871
Method and structure for a semiconductor fuse Apr 5, 2001 Issued
Array ( [id] => 6158106 [patent_doc_number] => 20020146914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-10 [patent_title] => 'In-situ steam generation process for nitrided oxide' [patent_app_type] => new [patent_app_number] => 09/828657 [patent_app_country] => US [patent_app_date] => 2001-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2170 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20020146914.pdf [firstpage_image] =>[orig_patent_app_number] => 09828657 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/828657
In-situ steam generation process for nitrided oxide Apr 5, 2001 Abandoned
09/807067 Salicide process for mosfet integrated circuit Apr 5, 2001 Abandoned
Array ( [id] => 1059559 [patent_doc_number] => 06852649 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-08 [patent_title] => 'Multi-step high density plasma (HDP) process to obtain uniformly doped insulating film' [patent_app_type] => utility [patent_app_number] => 09/823839 [patent_app_country] => US [patent_app_date] => 2001-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3657 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/852/06852649.pdf [firstpage_image] =>[orig_patent_app_number] => 09823839 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/823839
Multi-step high density plasma (HDP) process to obtain uniformly doped insulating film Mar 29, 2001 Issued
Array ( [id] => 7076921 [patent_doc_number] => 20010040265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-15 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => new [patent_app_number] => 09/820217 [patent_app_country] => US [patent_app_date] => 2001-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2084 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20010040265.pdf [firstpage_image] =>[orig_patent_app_number] => 09820217 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/820217
Semiconductor device and method for manufacturing the same Mar 28, 2001 Issued
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