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Stephen W. Smoot

Examiner (ID: 4681)

Most Active Art Unit
2813
Art Unit(s)
2813
Total Applications
1918
Issued Applications
1744
Pending Applications
33
Abandoned Applications
142

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14920831 [patent_doc_number] => 10431744 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-01 [patent_title] => Method of manufacturing organic light-emitting display apparatus using barrier layer having high fluorine content [patent_app_type] => utility [patent_app_number] => 15/884241 [patent_app_country] => US [patent_app_date] => 2018-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 36 [patent_no_of_words] => 8761 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15884241 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/884241
Method of manufacturing organic light-emitting display apparatus using barrier layer having high fluorine content Jan 29, 2018 Issued
Array ( [id] => 14676465 [patent_doc_number] => 20190237347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => INTEGRATED ELASTOMERIC INTERFACE LAYER FORMATION AND SINGULATION FOR LIGHT EMITTING DIODES [patent_app_type] => utility [patent_app_number] => 15/884243 [patent_app_country] => US [patent_app_date] => 2018-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5862 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15884243 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/884243
Integrated elastomeric interface layer formation and singulation for light emitting diodes Jan 29, 2018 Issued
Array ( [id] => 12823759 [patent_doc_number] => 20180166425 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-14 [patent_title] => LIGHT-EMITTING DIODE (LED) DEVICE [patent_app_type] => utility [patent_app_number] => 15/878720 [patent_app_country] => US [patent_app_date] => 2018-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20439 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15878720 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/878720
Light-emitting diode (LED) device Jan 23, 2018 Issued
Array ( [id] => 15890035 [patent_doc_number] => 10651376 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-12 [patent_title] => Method of manufacturing a memory device [patent_app_type] => utility [patent_app_number] => 15/878036 [patent_app_country] => US [patent_app_date] => 2018-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 19 [patent_no_of_words] => 6606 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15878036 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/878036
Method of manufacturing a memory device Jan 22, 2018 Issued
Array ( [id] => 14707597 [patent_doc_number] => 10381561 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-13 [patent_title] => Dedicated contacts for controlled electroforming of memory cells in resistive random-access memory array [patent_app_type] => utility [patent_app_number] => 15/867044 [patent_app_country] => US [patent_app_date] => 2018-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 6382 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15867044 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/867044
Dedicated contacts for controlled electroforming of memory cells in resistive random-access memory array Jan 9, 2018 Issued
Array ( [id] => 14460081 [patent_doc_number] => 10326015 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Switching element and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/855081 [patent_app_country] => US [patent_app_date] => 2017-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 9824 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 393 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15855081 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/855081
Switching element and method of manufacturing the same Dec 26, 2017 Issued
Array ( [id] => 12896284 [patent_doc_number] => 20180190603 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => CONTACT HOLE STRUCTURE AND FABRICATING METHOD OF CONTACT HOLE AND FUSE HOLE [patent_app_type] => utility [patent_app_number] => 15/854785 [patent_app_country] => US [patent_app_date] => 2017-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4030 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15854785 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/854785
Contact hole structure and fabricating method of contact hole and fuse hole Dec 26, 2017 Issued
Array ( [id] => 12692941 [patent_doc_number] => 20180122813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => THRESHOLD VOLTAGE MODULATION THROUGH CHANNEL LENGTH ADJUSTMENT [patent_app_type] => utility [patent_app_number] => 15/848433 [patent_app_country] => US [patent_app_date] => 2017-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6266 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15848433 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/848433
Threshold voltage modulation through channel length adjustment Dec 19, 2017 Issued
Array ( [id] => 12872338 [patent_doc_number] => 20180182621 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-28 [patent_title] => METHOD OF MANUFACTURING SWITCHING ELEMENT [patent_app_type] => utility [patent_app_number] => 15/842249 [patent_app_country] => US [patent_app_date] => 2017-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6243 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15842249 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/842249
Method of manufacturing switching element having gallium nitride substrate Dec 13, 2017 Issued
Array ( [id] => 14827833 [patent_doc_number] => 10410931 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-10 [patent_title] => Fabricating method of nanosheet transistor spacer including inner spacer [patent_app_type] => utility [patent_app_number] => 15/837613 [patent_app_country] => US [patent_app_date] => 2017-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 2733 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15837613 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/837613
Fabricating method of nanosheet transistor spacer including inner spacer Dec 10, 2017 Issued
Array ( [id] => 15000397 [patent_doc_number] => 20190319156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-17 [patent_title] => RADIATION-HARD HIGH-SPEED PHOTODIODE DEVICE [patent_app_type] => utility [patent_app_number] => 16/464806 [patent_app_country] => US [patent_app_date] => 2017-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3213 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16464806 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/464806
Radiation-hard high-speed photodiode device Nov 27, 2017 Issued
Array ( [id] => 12263820 [patent_doc_number] => 20180083017 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'THRESHOLD VOLTAGE MODULATION THROUGH CHANNEL LENGTH ADJUSTMENT' [patent_app_type] => utility [patent_app_number] => 15/823022 [patent_app_country] => US [patent_app_date] => 2017-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6568 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15823022 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/823022
Threshold voltage modulation through channel length adjustment Nov 26, 2017 Issued
Array ( [id] => 12759337 [patent_doc_number] => 20180144947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => PHOTOMASK MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 15/816673 [patent_app_country] => US [patent_app_date] => 2017-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3731 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15816673 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/816673
Photomask manufacturing method Nov 16, 2017 Issued
Array ( [id] => 14151593 [patent_doc_number] => 10256186 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-09 [patent_title] => Interconnect structure having subtractive etch feature and damascene feature [patent_app_type] => utility [patent_app_number] => 15/816508 [patent_app_country] => US [patent_app_date] => 2017-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 25 [patent_no_of_words] => 5044 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15816508 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/816508
Interconnect structure having subtractive etch feature and damascene feature Nov 16, 2017 Issued
Array ( [id] => 14558119 [patent_doc_number] => 10347530 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-09 [patent_title] => Method of forming interconnect structure with partial copper plating [patent_app_type] => utility [patent_app_number] => 15/816973 [patent_app_country] => US [patent_app_date] => 2017-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2678 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15816973 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/816973
Method of forming interconnect structure with partial copper plating Nov 16, 2017 Issued
Array ( [id] => 14706917 [patent_doc_number] => 10381217 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-13 [patent_title] => Method of depositing a thin film [patent_app_type] => utility [patent_app_number] => 15/816430 [patent_app_country] => US [patent_app_date] => 2017-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 2099 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15816430 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/816430
Method of depositing a thin film Nov 16, 2017 Issued
Array ( [id] => 13043209 [patent_doc_number] => 10043744 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-07 [patent_title] => Avoiding gate metal via shorting to source or drain contacts [patent_app_type] => utility [patent_app_number] => 15/800154 [patent_app_country] => US [patent_app_date] => 2017-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7728 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15800154 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/800154
Avoiding gate metal via shorting to source or drain contacts Oct 31, 2017 Issued
Array ( [id] => 13211321 [patent_doc_number] => 10120025 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-06 [patent_title] => Functional core circuitry with serial scan test expected, mask circuitry [patent_app_type] => utility [patent_app_number] => 15/795943 [patent_app_country] => US [patent_app_date] => 2017-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 47 [patent_no_of_words] => 14316 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15795943 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/795943
Functional core circuitry with serial scan test expected, mask circuitry Oct 26, 2017 Issued
Array ( [id] => 13976677 [patent_doc_number] => 10217704 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-02-26 [patent_title] => Method for simultaneous modification of multiple semiconductor device features [patent_app_type] => utility [patent_app_number] => 15/794403 [patent_app_country] => US [patent_app_date] => 2017-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5795 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15794403 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/794403
Method for simultaneous modification of multiple semiconductor device features Oct 25, 2017 Issued
Array ( [id] => 13293559 [patent_doc_number] => 10157980 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-12-18 [patent_title] => Semiconductor device having diode devices with different barrier heights and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 15/793439 [patent_app_country] => US [patent_app_date] => 2017-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7433 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15793439 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/793439
Semiconductor device having diode devices with different barrier heights and manufacturing method thereof Oct 24, 2017 Issued
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