Stephen W. Smoot

Array ( [id] => 13243453 [patent_doc_number] => 10134938 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-20 [patent_title] => Lateral avalanche photodetector [patent_app_type] => utility [patent_app_number] => 15/664856 [patent_app_country] => US [patent_app_date] => 2017-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4557 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15664856 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12680191 [patent_doc_number] => 20180118563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => METHOD FOR CHARACTERIZING CARBON NANOTUBES [patent_app_type] => utility [patent_app_number] => 15/661061 [patent_app_country] => US [patent_app_date] => 2017-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1912 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15661061 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13257465 [patent_doc_number] => 10141430 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-11-27 [patent_title] => Fin structures with uniform threshold voltage distribution and method of making the same [patent_app_type] => utility [patent_app_number] => 15/661037 [patent_app_country] => US [patent_app_date] => 2017-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6411 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15661037 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12294123 [patent_doc_number] => 09935062 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-03 [patent_title] => Backside fib probing detector in a forward and reverse body biasing architecture [patent_app_type] => utility [patent_app_number] => 15/661369 [patent_app_country] => US [patent_app_date] => 2017-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 3170 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15661369 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14389247 [patent_doc_number] => 10307884 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-04 [patent_title] => Apparatus for controlling a movement of a grinding wheel, semiconductor wafer grinding system and method for forming semiconductor devices [patent_app_type] => utility [patent_app_number] => 15/655477 [patent_app_country] => US [patent_app_date] => 2017-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 7379 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15655477 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15462651 [patent_doc_number] => 20200044150 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-06 [patent_title] => MULTIPLE SILICON ATOM QUANTUM DOT AND DEVICES INCLUSIVE THEREOF [patent_app_type] => utility [patent_app_number] => 16/318626 [patent_app_country] => US [patent_app_date] => 2017-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15506 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16318626 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13030861 [patent_doc_number] => 10038055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-31 [patent_title] => Substrate structure with embedded layer for post-processing silicon handle elimination [patent_app_type] => utility [patent_app_number] => 15/648082 [patent_app_country] => US [patent_app_date] => 2017-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 3387 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15648082 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13030861 [patent_doc_number] => 10038055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-31 [patent_title] => Substrate structure with embedded layer for post-processing silicon handle elimination [patent_app_type] => utility [patent_app_number] => 15/648082 [patent_app_country] => US [patent_app_date] => 2017-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 3387 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15648082 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13030861 [patent_doc_number] => 10038055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-31 [patent_title] => Substrate structure with embedded layer for post-processing silicon handle elimination [patent_app_type] => utility [patent_app_number] => 15/648082 [patent_app_country] => US [patent_app_date] => 2017-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 3387 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15648082 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13030861 [patent_doc_number] => 10038055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-31 [patent_title] => Substrate structure with embedded layer for post-processing silicon handle elimination [patent_app_type] => utility [patent_app_number] => 15/648082 [patent_app_country] => US [patent_app_date] => 2017-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 3387 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15648082 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13030861 [patent_doc_number] => 10038055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-31 [patent_title] => Substrate structure with embedded layer for post-processing silicon handle elimination [patent_app_type] => utility [patent_app_number] => 15/648082 [patent_app_country] => US [patent_app_date] => 2017-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 3387 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15648082 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13030861 [patent_doc_number] => 10038055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-31 [patent_title] => Substrate structure with embedded layer for post-processing silicon handle elimination [patent_app_type] => utility [patent_app_number] => 15/648082 [patent_app_country] => US [patent_app_date] => 2017-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 3387 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15648082 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13030861 [patent_doc_number] => 10038055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-31 [patent_title] => Substrate structure with embedded layer for post-processing silicon handle elimination [patent_app_type] => utility [patent_app_number] => 15/648082 [patent_app_country] => US [patent_app_date] => 2017-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 3387 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15648082 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13030861 [patent_doc_number] => 10038055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-31 [patent_title] => Substrate structure with embedded layer for post-processing silicon handle elimination [patent_app_type] => utility [patent_app_number] => 15/648082 [patent_app_country] => US [patent_app_date] => 2017-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 3387 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15648082 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13030861 [patent_doc_number] => 10038055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-31 [patent_title] => Substrate structure with embedded layer for post-processing silicon handle elimination [patent_app_type] => utility [patent_app_number] => 15/648082 [patent_app_country] => US [patent_app_date] => 2017-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 3387 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15648082 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12631272 [patent_doc_number] => 20180102254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-12 [patent_title] => Method of Wet Etching and Method of Fabricating Semiconductor Device Using the Same [patent_app_type] => utility [patent_app_number] => 15/645419 [patent_app_country] => US [patent_app_date] => 2017-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8734 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15645419 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16218729 [patent_doc_number] => 10734552 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-04 [patent_title] => Semiconductor device having a light emitting structure [patent_app_type] => utility [patent_app_number] => 16/310340 [patent_app_country] => US [patent_app_date] => 2017-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 56 [patent_no_of_words] => 28165 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16310340 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11979100 [patent_doc_number] => 20170283254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) ULTRASONIC TRANSDUCERS AND METHODS FOR FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/626801 [patent_app_country] => US [patent_app_date] => 2017-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 16505 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15626801 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14667955 [patent_doc_number] => 10371874 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-06 [patent_title] => Substrate unit of nanostructure assembly type, optical imaging apparatus including the same, and controlling method thereof [patent_app_type] => utility [patent_app_number] => 15/626778 [patent_app_country] => US [patent_app_date] => 2017-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5232 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15626778 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13629543 [patent_doc_number] => 20180366324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => REPLACEMENT CONTACT CUTS WITH AN ENCAPSULATED LOW-K DIELECTRIC [patent_app_type] => utility [patent_app_number] => 15/626732 [patent_app_country] => US [patent_app_date] => 2017-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3379 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15626732 [rel_patent_id] =>[rel_patent_doc_number] =>)