| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 16172946
[patent_doc_number] => 10714524
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-07-14
[patent_title] => Circuit board, semiconductor device, imaging device, solid-state image sensor, method for manufacturing solid-state image sensor, and electronic apparatus
[patent_app_type] => utility
[patent_app_number] => 16/086904
[patent_app_country] => US
[patent_app_date] => 2017-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 16
[patent_no_of_words] => 8684
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16086904
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/086904 | Circuit board, semiconductor device, imaging device, solid-state image sensor, method for manufacturing solid-state image sensor, and electronic apparatus | Mar 14, 2017 | Issued |
Array
(
[id] => 15984939
[patent_doc_number] => 10672809
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-06-02
[patent_title] => Solid-state imaging apparatus having output circuit unit for outputting pixel signal
[patent_app_type] => utility
[patent_app_number] => 16/086404
[patent_app_country] => US
[patent_app_date] => 2017-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 82
[patent_figures_cnt] => 82
[patent_no_of_words] => 31842
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16086404
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/086404 | Solid-state imaging apparatus having output circuit unit for outputting pixel signal | Mar 14, 2017 | Issued |
Array
(
[id] => 16264685
[patent_doc_number] => 10756132
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-08-25
[patent_title] => Solid-state imaging device, method of manufacturing the same, and electronic apparatus
[patent_app_type] => utility
[patent_app_number] => 16/086627
[patent_app_country] => US
[patent_app_date] => 2017-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 18
[patent_no_of_words] => 8694
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16086627
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/086627 | Solid-state imaging device, method of manufacturing the same, and electronic apparatus | Mar 14, 2017 | Issued |
Array
(
[id] => 13936517
[patent_doc_number] => 20190051774
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-02-14
[patent_title] => CONDUCTIVE PASTE COMPRISING A SILICONE OIL
[patent_app_type] => utility
[patent_app_number] => 16/078176
[patent_app_country] => US
[patent_app_date] => 2017-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4309
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16078176
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/078176 | Conductive paste comprising a silicone oil | Feb 22, 2017 | Issued |
Array
(
[id] => 11728718
[patent_doc_number] => 20170190161
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-07-06
[patent_title] => 'INORGANIC MULTILAYER LAMINATION TRANSFER FILMS'
[patent_app_type] => utility
[patent_app_number] => 15/411436
[patent_app_country] => US
[patent_app_date] => 2017-01-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 10499
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15411436
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/411436 | Inorganic multilayer lamination transfer films | Jan 19, 2017 | Issued |
Array
(
[id] => 11840095
[patent_doc_number] => 20170221815
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-08-03
[patent_title] => 'INTERCONNECT SCALING'
[patent_app_type] => utility
[patent_app_number] => 15/405344
[patent_app_country] => US
[patent_app_date] => 2017-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 5035
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15405344
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/405344 | Interconnect structure having substractive etch feature and damascene feature | Jan 12, 2017 | Issued |
Array
(
[id] => 11594445
[patent_doc_number] => 20170118856
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-04-27
[patent_title] => 'METHOD FOR PRODUCING A HERMETIC HOUSING FOR AN ELECTRONIC DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/398317
[patent_app_country] => US
[patent_app_date] => 2017-01-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 13294
[patent_no_of_claims] => 57
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15398317
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/398317 | METHOD FOR PRODUCING A HERMETIC HOUSING FOR AN ELECTRONIC DEVICE | Jan 3, 2017 | Abandoned |
Array
(
[id] => 11758674
[patent_doc_number] => 20170205543
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-07-20
[patent_title] => 'MIRROR SUBSTRATES, METHODS OF MANUFACTURING THE SAME AND DISPLAY DEVICES INCLUDING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 15/397606
[patent_app_country] => US
[patent_app_date] => 2017-01-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 8902
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15397606
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/397606 | Mirror substrates, methods of manufacturing the same and display devices including the same | Jan 2, 2017 | Issued |
Array
(
[id] => 13132305
[patent_doc_number] => 10084092
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-09-25
[patent_title] => Method for fabricating FinFET structure
[patent_app_type] => utility
[patent_app_number] => 15/397584
[patent_app_country] => US
[patent_app_date] => 2017-01-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 11
[patent_no_of_words] => 2614
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15397584
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/397584 | Method for fabricating FinFET structure | Jan 2, 2017 | Issued |
Array
(
[id] => 14178101
[patent_doc_number] => 10263073
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-04-16
[patent_title] => III-V semiconductor layers, III-V semiconductor devices and methods of manufacturing thereof
[patent_app_type] => utility
[patent_app_number] => 15/397508
[patent_app_country] => US
[patent_app_date] => 2017-01-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 46
[patent_no_of_words] => 6654
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15397508
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/397508 | III-V semiconductor layers, III-V semiconductor devices and methods of manufacturing thereof | Jan 2, 2017 | Issued |
Array
(
[id] => 13976675
[patent_doc_number] => 10217703
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-02-26
[patent_title] => Circuits for and methods of implementing an inductor and a pattern ground shield in an integrated circuit
[patent_app_type] => utility
[patent_app_number] => 15/397612
[patent_app_country] => US
[patent_app_date] => 2017-01-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 15
[patent_no_of_words] => 5271
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15397612
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/397612 | Circuits for and methods of implementing an inductor and a pattern ground shield in an integrated circuit | Jan 2, 2017 | Issued |
Array
(
[id] => 15030417
[patent_doc_number] => 20190326213
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-10-24
[patent_title] => MICROELECTRONIC DEVICES DESIGNED WITH CAPACITIVE AND ENHANCED INDUCTIVE BUMPS
[patent_app_type] => utility
[patent_app_number] => 16/464972
[patent_app_country] => US
[patent_app_date] => 2016-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3702
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 45
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16464972
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/464972 | Microelectronic devices designed with capacitive and enhanced inductive bumps | Dec 29, 2016 | Issued |
Array
(
[id] => 11732841
[patent_doc_number] => 20170194284
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-07-06
[patent_title] => 'METHOD AND DEVICE FOR IMPROVED DIE BONDING'
[patent_app_type] => utility
[patent_app_number] => 15/394609
[patent_app_country] => US
[patent_app_date] => 2016-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3693
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15394609
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/394609 | Method and device for improved die bonding | Dec 28, 2016 | Issued |
Array
(
[id] => 12047589
[patent_doc_number] => 09825199
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-11-21
[patent_title] => 'Laser-transferred IBC solar cells'
[patent_app_type] => utility
[patent_app_number] => 15/392163
[patent_app_country] => US
[patent_app_date] => 2016-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 6405
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15392163
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/392163 | Laser-transferred IBC solar cells | Dec 27, 2016 | Issued |
Array
(
[id] => 12931048
[patent_doc_number] => 09829538
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-11-28
[patent_title] => IC expected data and mask data on I/O data pads
[patent_app_type] => utility
[patent_app_number] => 15/388470
[patent_app_country] => US
[patent_app_date] => 2016-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 47
[patent_no_of_words] => 14294
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 281
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15388470
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/388470 | IC expected data and mask data on I/O data pads | Dec 21, 2016 | Issued |
Array
(
[id] => 11544722
[patent_doc_number] => 20170098547
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-04-06
[patent_title] => 'METHOD OF MODIFYING EPITAXIAL GROWTH SHAPE ON SOURCE DRAIN AREA OF TRANSISTOR'
[patent_app_type] => utility
[patent_app_number] => 15/384051
[patent_app_country] => US
[patent_app_date] => 2016-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3268
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15384051
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/384051 | Method of modifying epitaxial growth shape on source drain area of transistor | Dec 18, 2016 | Issued |
Array
(
[id] => 16308670
[patent_doc_number] => 10777477
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-09-15
[patent_title] => Chip packaging structure, and packaging method thereof
[patent_app_type] => utility
[patent_app_number] => 16/330765
[patent_app_country] => US
[patent_app_date] => 2016-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 18
[patent_no_of_words] => 4389
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 304
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16330765
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/330765 | Chip packaging structure, and packaging method thereof | Dec 11, 2016 | Issued |
Array
(
[id] => 11571912
[patent_doc_number] => 20170110556
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-04-20
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 15/372758
[patent_app_country] => US
[patent_app_date] => 2016-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 10525
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15372758
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/372758 | Method of manufacturing semiconductor device that includes forming junction field effect transistor including recessed gate | Dec 7, 2016 | Issued |
Array
(
[id] => 11502963
[patent_doc_number] => 20170077148
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-03-16
[patent_title] => 'SEMICONDUCTOR DEVICE, ELECTRO-OPTICAL DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING ELECTRO-OPTICAL DEVICE, AND ELECTRONIC APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 15/363713
[patent_app_country] => US
[patent_app_date] => 2016-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 9576
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15363713
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/363713 | Semiconductor device having semiconductor layer that includes channel region formed into concave shape, electro-optical device, method of manufacturing semiconductor device, method of manufacturing electro-optical device, and electronic apparatus | Nov 28, 2016 | Issued |
Array
(
[id] => 15667149
[patent_doc_number] => 10597795
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-03-24
[patent_title] => Method for producing a semiconductor wafer with epitaxial layer in a deposition chamber, apparatus for producing a semiconductor wafer with epitaxial layer, and semiconductor wafer with epitaxial layer
[patent_app_type] => utility
[patent_app_number] => 15/778549
[patent_app_country] => US
[patent_app_date] => 2016-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5386
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15778549
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/778549 | Method for producing a semiconductor wafer with epitaxial layer in a deposition chamber, apparatus for producing a semiconductor wafer with epitaxial layer, and semiconductor wafer with epitaxial layer | Nov 23, 2016 | Issued |