Search

Stephen W. Smoot

Examiner (ID: 2594, Phone: (571)272-1698 , Office: P/2813 )

Most Active Art Unit
2813
Art Unit(s)
2813
Total Applications
1918
Issued Applications
1746
Pending Applications
33
Abandoned Applications
142

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11710528 [patent_doc_number] => 20170179027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'MEMORY DEVICE HAVING CELL OVER PERIPHERY STRUCTURE AND MEMORY PACKAGE INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/273268 [patent_app_country] => US [patent_app_date] => 2016-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 14147 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15273268 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/273268
Memory device having cell over periphery structure and memory package including the same Sep 21, 2016 Issued
Array ( [id] => 13112121 [patent_doc_number] => 10074721 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-11 [patent_title] => Method of fabricating a semiconductor wafer that includes producing a planarised surface having both a mesa surface and an insulating layer surface [patent_app_type] => utility [patent_app_number] => 15/273231 [patent_app_country] => US [patent_app_date] => 2016-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 5902 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15273231 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/273231
Method of fabricating a semiconductor wafer that includes producing a planarised surface having both a mesa surface and an insulating layer surface Sep 21, 2016 Issued
Array ( [id] => 11517532 [patent_doc_number] => 20170084606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'Integrated Circuit with a Plurality of Transistors and at Least One Voltage Limiting Structure' [patent_app_type] => utility [patent_app_number] => 15/273352 [patent_app_country] => US [patent_app_date] => 2016-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6867 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15273352 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/273352
Integrated Circuit with a Plurality of Transistors and at Least One Voltage Limiting Structure Sep 21, 2016 Abandoned
Array ( [id] => 11557845 [patent_doc_number] => 20170104091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-13 [patent_title] => 'NITRIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/273336 [patent_app_country] => US [patent_app_date] => 2016-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9208 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15273336 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/273336
Nitride semiconductor device and manufacturing method thereof Sep 21, 2016 Issued
Array ( [id] => 12263795 [patent_doc_number] => 20180082992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'INTEGRATED CIRCUIT WITH PROTECTION FROM TRANSIENT ELECTRICAL STRESS EVENTS AND METHOD THEREFOR' [patent_app_type] => utility [patent_app_number] => 15/273220 [patent_app_country] => US [patent_app_date] => 2016-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6683 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15273220 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/273220
Integrated circuit with protection from transient electrical stress events and method therefor Sep 21, 2016 Issued
Array ( [id] => 11740318 [patent_doc_number] => 09704912 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-11 [patent_title] => 'Semiconductor device and semiconductor device manufacturing method' [patent_app_type] => utility [patent_app_number] => 15/273139 [patent_app_country] => US [patent_app_date] => 2016-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 6015 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15273139 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/273139
Semiconductor device and semiconductor device manufacturing method Sep 21, 2016 Issued
Array ( [id] => 11891275 [patent_doc_number] => 09761844 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-12 [patent_title] => 'Lamination transfer films including oriented dimensionally anisotropic inorganic nanomaterials' [patent_app_type] => utility [patent_app_number] => 15/270627 [patent_app_country] => US [patent_app_date] => 2016-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 9535 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15270627 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/270627
Lamination transfer films including oriented dimensionally anisotropic inorganic nanomaterials Sep 19, 2016 Issued
Array ( [id] => 11366980 [patent_doc_number] => 20170004962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-05 [patent_title] => 'DOUBLE SIDED SI(GE)/SAPPHIRE/III-NITRIDE HYBRID STRUCTURE' [patent_app_type] => utility [patent_app_number] => 15/264034 [patent_app_country] => US [patent_app_date] => 2016-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3631 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15264034 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/264034
Method of fabricating double sided Si(Ge)/Sapphire/III-nitride hybrid structure Sep 12, 2016 Issued
Array ( [id] => 11545923 [patent_doc_number] => 20170099748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-06 [patent_title] => 'ROTATION CONTROL METHOD, INFORMATION PROCESSING DEVICE, AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM STORING ROTATION CONTROL PROGRAM' [patent_app_type] => utility [patent_app_number] => 15/253932 [patent_app_country] => US [patent_app_date] => 2016-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6909 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15253932 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/253932
Rotation control method, information processing device, and non-transitory computer-readable recording medium storing rotation control program Aug 31, 2016 Issued
Array ( [id] => 11681337 [patent_doc_number] => 09679872 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-06-13 [patent_title] => 'Connection structure for semiconductor package having plural vias located within projection of conductive unit' [patent_app_type] => utility [patent_app_number] => 15/253011 [patent_app_country] => US [patent_app_date] => 2016-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6891 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15253011 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/253011
Connection structure for semiconductor package having plural vias located within projection of conductive unit Aug 30, 2016 Issued
Array ( [id] => 11460021 [patent_doc_number] => 20170053927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-23 [patent_title] => 'One-Time Programmable Memory and Method for Making the Same' [patent_app_type] => utility [patent_app_number] => 15/250831 [patent_app_country] => US [patent_app_date] => 2016-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 4805 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15250831 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/250831
One-time programmable memory and method for making the same Aug 28, 2016 Issued
Array ( [id] => 15316961 [patent_doc_number] => 10523201 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Pane arrangement with pane with low-E coating and capacitive switching region [patent_app_type] => utility [patent_app_number] => 15/739691 [patent_app_country] => US [patent_app_date] => 2016-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 14049 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15739691 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/739691
Pane arrangement with pane with low-E coating and capacitive switching region Aug 17, 2016 Issued
Array ( [id] => 15783477 [patent_doc_number] => 10625443 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => Method and device for releasing resin film, method for manufacturing electronic device, and method for manufacturing organic EL display device [patent_app_type] => utility [patent_app_number] => 16/067216 [patent_app_country] => US [patent_app_date] => 2016-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 11218 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16067216 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/067216
Method and device for releasing resin film, method for manufacturing electronic device, and method for manufacturing organic EL display device Jul 21, 2016 Issued
Array ( [id] => 11884003 [patent_doc_number] => 09755189 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-05 [patent_title] => 'Method for forming projections and depressions, sealing structure, and light-emitting device' [patent_app_type] => utility [patent_app_number] => 15/211444 [patent_app_country] => US [patent_app_date] => 2016-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 46 [patent_no_of_words] => 15074 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15211444 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/211444
Method for forming projections and depressions, sealing structure, and light-emitting device Jul 14, 2016 Issued
Array ( [id] => 13346403 [patent_doc_number] => 20180224741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-09 [patent_title] => COMPOSITIONS AND METHODS FOR FORMING A PIXEL-DEFINING LAYER [patent_app_type] => utility [patent_app_number] => 15/747897 [patent_app_country] => US [patent_app_date] => 2016-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9459 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15747897 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/747897
COMPOSITIONS AND METHODS FOR FORMING A PIXEL-DEFINING LAYER Jul 10, 2016 Abandoned
Array ( [id] => 13364333 [patent_doc_number] => 20180233706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-16 [patent_title] => METHOD OF MANUFACTURING ORGANIC EL ELEMENT [patent_app_type] => utility [patent_app_number] => 15/747816 [patent_app_country] => US [patent_app_date] => 2016-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4077 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15747816 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/747816
Method of manufacturing organic EL element Jul 7, 2016 Issued
Array ( [id] => 11876562 [patent_doc_number] => 09748344 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-29 [patent_title] => 'Nitride semiconductor substrate having recesses at interface between base substrate and initial nitride' [patent_app_type] => utility [patent_app_number] => 15/202736 [patent_app_country] => US [patent_app_date] => 2016-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 6586 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15202736 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/202736
Nitride semiconductor substrate having recesses at interface between base substrate and initial nitride Jul 5, 2016 Issued
Array ( [id] => 12040442 [patent_doc_number] => 09818677 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-14 [patent_title] => 'Semiconductor component having group III nitride semiconductor device mounted on substrate and interconnected to lead frame' [patent_app_type] => utility [patent_app_number] => 15/202765 [patent_app_country] => US [patent_app_date] => 2016-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 28 [patent_no_of_words] => 7630 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15202765 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/202765
Semiconductor component having group III nitride semiconductor device mounted on substrate and interconnected to lead frame Jul 5, 2016 Issued
Array ( [id] => 12047312 [patent_doc_number] => 09824921 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-11-21 [patent_title] => 'Method and apparatus for placing a gate contact inside a semiconductor active region having high-k dielectric gate caps' [patent_app_type] => utility [patent_app_number] => 15/202817 [patent_app_country] => US [patent_app_date] => 2016-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 5057 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15202817 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/202817
Method and apparatus for placing a gate contact inside a semiconductor active region having high-k dielectric gate caps Jul 5, 2016 Issued
Array ( [id] => 12129300 [patent_doc_number] => 20180012887 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-11 [patent_title] => 'METHOD AND APPARATUS FOR PLACING A GATE CONTACT INSIDE AN ACTIVE REGION OF A SEMICONDUCTOR' [patent_app_type] => utility [patent_app_number] => 15/202764 [patent_app_country] => US [patent_app_date] => 2016-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5171 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15202764 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/202764
Method and apparatus for placing a gate contact inside an active region of a semiconductor Jul 5, 2016 Issued
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