Search

Stephen W. Smoot

Examiner (ID: 13733, Phone: (571)272-1698 , Office: P/2813 )

Most Active Art Unit
2813
Art Unit(s)
2813
Total Applications
1918
Issued Applications
1746
Pending Applications
33
Abandoned Applications
142

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11110142 [patent_doc_number] => 20160307112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-20 [patent_title] => 'ATOMISTIC QUANTUM DOTS' [patent_app_type] => utility [patent_app_number] => 15/195459 [patent_app_country] => US [patent_app_date] => 2016-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8893 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15195459 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/195459
Method for operating an electronic state device by perturbating dangling bond electronic states Jun 27, 2016 Issued
Array ( [id] => 11584288 [patent_doc_number] => 09638922 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-02 [patent_title] => 'High-efficiency line-forming optical systems and methods' [patent_app_type] => utility [patent_app_number] => 15/191941 [patent_app_country] => US [patent_app_date] => 2016-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6905 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15191941 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/191941
High-efficiency line-forming optical systems and methods Jun 23, 2016 Issued
Array ( [id] => 11539643 [patent_doc_number] => 09614061 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-04 [patent_title] => 'Semiconductor device having fin structure that includes dummy fins' [patent_app_type] => utility [patent_app_number] => 15/188998 [patent_app_country] => US [patent_app_date] => 2016-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2165 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15188998 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/188998
Semiconductor device having fin structure that includes dummy fins Jun 21, 2016 Issued
Array ( [id] => 11103909 [patent_doc_number] => 20160300878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-13 [patent_title] => 'IMAGING DEVICE AND IMAGING SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/188009 [patent_app_country] => US [patent_app_date] => 2016-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7613 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15188009 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/188009
Imaging device having electrode overlying photoelectric conversion layer and having electrical contact to electrode Jun 20, 2016 Issued
Array ( [id] => 12095528 [patent_doc_number] => 20170352621 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-07 [patent_title] => 'AVOIDING GATE METAL VIA SHORTING TO SOURCE OR DRAIN CONTACTS' [patent_app_type] => utility [patent_app_number] => 15/175555 [patent_app_country] => US [patent_app_date] => 2016-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 7905 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15175555 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/175555
Avoiding gate metal via shorting to source or drain contacts Jun 6, 2016 Issued
Array ( [id] => 12416850 [patent_doc_number] => 09972565 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-05-15 [patent_title] => Lateral vias for connections to buried microconductors [patent_app_type] => utility [patent_app_number] => 15/175312 [patent_app_country] => US [patent_app_date] => 2016-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 23 [patent_no_of_words] => 12341 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15175312 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/175312
Lateral vias for connections to buried microconductors Jun 6, 2016 Issued
Array ( [id] => 12019686 [patent_doc_number] => 09812396 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-11-07 [patent_title] => 'Interconnect structure for semiconductor devices with multiple power rails and redundancy' [patent_app_type] => utility [patent_app_number] => 15/175495 [patent_app_country] => US [patent_app_date] => 2016-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 3280 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15175495 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/175495
Interconnect structure for semiconductor devices with multiple power rails and redundancy Jun 6, 2016 Issued
Array ( [id] => 11932552 [patent_doc_number] => 09799555 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-10-24 [patent_title] => 'Cobalt interconnects covered by a metal cap' [patent_app_type] => utility [patent_app_number] => 15/175573 [patent_app_country] => US [patent_app_date] => 2016-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 5536 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15175573 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/175573
Cobalt interconnects covered by a metal cap Jun 6, 2016 Issued
Array ( [id] => 11079391 [patent_doc_number] => 20160276354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-22 [patent_title] => 'SALICIDED STRUCTURE TO INTEGRATE A FLASH MEMORY DEVICE WITH A HIGH K, METAL GATE LOGIC DEVICE' [patent_app_type] => utility [patent_app_number] => 15/170104 [patent_app_country] => US [patent_app_date] => 2016-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 12974 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15170104 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/170104
Salicided structure to integrate a flash memory device with a high K, metal gate logic device May 31, 2016 Issued
Array ( [id] => 11524678 [patent_doc_number] => 09608090 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-28 [patent_title] => 'Method for fabricating semiconductor device having fin structure that includes dummy fins' [patent_app_type] => utility [patent_app_number] => 15/170904 [patent_app_country] => US [patent_app_date] => 2016-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2164 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15170904 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/170904
Method for fabricating semiconductor device having fin structure that includes dummy fins May 31, 2016 Issued
Array ( [id] => 13159671 [patent_doc_number] => 10096570 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-09 [patent_title] => Manufacturing method for power semiconductor device, and power semiconductor device [patent_app_type] => utility [patent_app_number] => 15/568130 [patent_app_country] => US [patent_app_date] => 2016-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 26 [patent_no_of_words] => 7817 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15568130 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/568130
Manufacturing method for power semiconductor device, and power semiconductor device May 30, 2016 Issued
Array ( [id] => 11510260 [patent_doc_number] => 09601426 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-03-21 [patent_title] => 'Interconnect structure having subtractive etch feature and damascene feature' [patent_app_type] => utility [patent_app_number] => 15/166570 [patent_app_country] => US [patent_app_date] => 2016-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 25 [patent_no_of_words] => 5012 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15166570 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/166570
Interconnect structure having subtractive etch feature and damascene feature May 26, 2016 Issued
Array ( [id] => 11740279 [patent_doc_number] => 09704873 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-11 [patent_title] => 'Semiconductor device including memory cell array with transistors disposed in different active regions' [patent_app_type] => utility [patent_app_number] => 15/165651 [patent_app_country] => US [patent_app_date] => 2016-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 63 [patent_figures_cnt] => 65 [patent_no_of_words] => 32998 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 349 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15165651 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/165651
Semiconductor device including memory cell array with transistors disposed in different active regions May 25, 2016 Issued
Array ( [id] => 13327177 [patent_doc_number] => 20180215126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-02 [patent_title] => METHOD FOR SUPPLYING AN ELECTRONIC COMPONENT OF A LAMINATED GLAZING UNIT WITH ELECTRICAL POWER AND LAMINATED GLAZING UNIT FOR IMPLEMENTING SAID METHOD [patent_app_type] => utility [patent_app_number] => 15/578390 [patent_app_country] => US [patent_app_date] => 2016-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3921 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15578390 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/578390
Method for supplying an electronic component of a laminated glazing unit with electrical power and laminated glazing unit for implementing said method May 16, 2016 Issued
Array ( [id] => 11050978 [patent_doc_number] => 20160247937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-25 [patent_title] => 'THIN FILM TRANSISTOR SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 15/147610 [patent_app_country] => US [patent_app_date] => 2016-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4577 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15147610 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/147610
Thin film transistor substrate May 4, 2016 Issued
Array ( [id] => 11904276 [patent_doc_number] => 09773716 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-26 [patent_title] => 'Systems and methods to enhance passivation integrity' [patent_app_type] => utility [patent_app_number] => 15/146012 [patent_app_country] => US [patent_app_date] => 2016-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 4003 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15146012 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/146012
Systems and methods to enhance passivation integrity May 3, 2016 Issued
Array ( [id] => 11990423 [patent_doc_number] => 20170294578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-12 [patent_title] => 'PHASE CHANGE STORAGE DEVICE WITH MULTIPLE SERIALLY CONNECTED STORAGE REGIONS' [patent_app_type] => utility [patent_app_number] => 15/095023 [patent_app_country] => US [patent_app_date] => 2016-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3314 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15095023 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/095023
Phase change storage device with multiple serially connected storage regions Apr 8, 2016 Issued
Array ( [id] => 12202688 [patent_doc_number] => 09905762 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-27 [patent_title] => 'Display substrate and fabricating method thereof, and system for fabricating display substrate and display device' [patent_app_type] => utility [patent_app_number] => 15/511309 [patent_app_country] => US [patent_app_date] => 2016-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5176 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15511309 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/511309
Display substrate and fabricating method thereof, and system for fabricating display substrate and display device Mar 31, 2016 Issued
Array ( [id] => 13963541 [patent_doc_number] => 20190058115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-21 [patent_title] => PROGRAMMABLE METALLIZATION CELL WITH ALLOY LAYER [patent_app_type] => utility [patent_app_number] => 16/077760 [patent_app_country] => US [patent_app_date] => 2016-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6331 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16077760 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/077760
Programmable metallization cell with alloy layer Mar 30, 2016 Issued
Array ( [id] => 11132384 [patent_doc_number] => 20160329360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-10 [patent_title] => 'LOW TEMPERATURE POLY-SILICON THIN FILM TRANSISTOR, FABRICATING METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/085217 [patent_app_country] => US [patent_app_date] => 2016-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3760 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15085217 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/085217
Low temperature poly-silicon thin film transistor, fabricating method thereof, array substrate and display device Mar 29, 2016 Issued
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