
Stephen W. Smoot
Examiner (ID: 13733, Phone: (571)272-1698 , Office: P/2813 )
| Most Active Art Unit | 2813 |
| Art Unit(s) | 2813 |
| Total Applications | 1918 |
| Issued Applications | 1746 |
| Pending Applications | 33 |
| Abandoned Applications | 142 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 11110142
[patent_doc_number] => 20160307112
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[patent_title] => 'ATOMISTIC QUANTUM DOTS'
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Array
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Array
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Array
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Array
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[patent_title] => 'SALICIDED STRUCTURE TO INTEGRATE A FLASH MEMORY DEVICE WITH A HIGH K, METAL GATE LOGIC DEVICE'
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Array
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Array
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Array
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Array
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