Search

Steve Rowland

Examiner (ID: 96, Phone: (469)295-9129 , Office: P/3716 )

Most Active Art Unit
3715
Art Unit(s)
3718, 3716, 3714, 3715
Total Applications
1154
Issued Applications
865
Pending Applications
81
Abandoned Applications
240

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9875970 [patent_doc_number] => 08963242 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-24 [patent_title] => 'Power semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/787603 [patent_app_country] => US [patent_app_date] => 2013-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 8914 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13787603 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/787603
Power semiconductor device Mar 5, 2013 Issued
Array ( [id] => 9869746 [patent_doc_number] => 08957522 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-17 [patent_title] => 'Semiconductor device and manufacturing method of semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/787526 [patent_app_country] => US [patent_app_date] => 2013-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 29 [patent_no_of_words] => 12718 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13787526 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/787526
Semiconductor device and manufacturing method of semiconductor device Mar 5, 2013 Issued
Array ( [id] => 9367382 [patent_doc_number] => 20140077255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-20 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/787735 [patent_app_country] => US [patent_app_date] => 2013-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5426 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13787735 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/787735
SEMICONDUCTOR DEVICE Mar 5, 2013 Abandoned
Array ( [id] => 9171659 [patent_doc_number] => 20130313644 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-28 [patent_title] => 'SWITCHING CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/787744 [patent_app_country] => US [patent_app_date] => 2013-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4720 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13787744 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/787744
Switching circuit Mar 5, 2013 Issued
Array ( [id] => 8901246 [patent_doc_number] => 20130168749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-04 [patent_title] => 'BORDERLESS CONTACT STRUCTURE EMPLOYING DUAL ETCH STOP LAYERS' [patent_app_type] => utility [patent_app_number] => 13/777410 [patent_app_country] => US [patent_app_date] => 2013-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7791 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13777410 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/777410
Borderless contact structure employing dual etch stop layers Feb 25, 2013 Issued
Array ( [id] => 8841630 [patent_doc_number] => 20130137258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-30 [patent_title] => 'METHOD FOR FABRICATING BURIED GATES USING PRE LANDING PLUGS' [patent_app_type] => utility [patent_app_number] => 13/745387 [patent_app_country] => US [patent_app_date] => 2013-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 7677 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13745387 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/745387
Method for fabricating buried gates using pre landing plugs Jan 17, 2013 Issued
Array ( [id] => 9171702 [patent_doc_number] => 20130313687 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-28 [patent_title] => 'Through via/the buried via elrctrolde material and the said via structure and the said via manufacturing method' [patent_app_type] => utility [patent_app_number] => 13/740688 [patent_app_country] => US [patent_app_date] => 2013-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11375 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13740688 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/740688
Through via/the buried via elrctrolde material and the said via structure and the said via manufacturing method Jan 13, 2013 Abandoned
Array ( [id] => 8863195 [patent_doc_number] => 20130146898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-13 [patent_title] => 'SiC MOSFETS AND SELF-ALIGNED FABRICATION METHODS THEREOF' [patent_app_type] => utility [patent_app_number] => 13/740734 [patent_app_country] => US [patent_app_date] => 2013-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6642 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13740734 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/740734
SiC MOSFETS AND SELF-ALIGNED FABRICATION METHODS THEREOF Jan 13, 2013 Abandoned
Array ( [id] => 8821617 [patent_doc_number] => 20130122662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-16 [patent_title] => 'ELECTRONIC COMPONENT AND METHOD OF MANUFACTURING ELECTRONIC COMPONENT' [patent_app_type] => utility [patent_app_number] => 13/737788 [patent_app_country] => US [patent_app_date] => 2013-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11284 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13737788 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/737788
ELECTRONIC COMPONENT AND METHOD OF MANUFACTURING ELECTRONIC COMPONENT Jan 8, 2013 Abandoned
Array ( [id] => 8821615 [patent_doc_number] => 20130122660 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-16 [patent_title] => 'SENSOR DEVICE AND METHOD' [patent_app_type] => utility [patent_app_number] => 13/733375 [patent_app_country] => US [patent_app_date] => 2013-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6703 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13733375 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/733375
Sensor device and method Jan 2, 2013 Issued
Array ( [id] => 10882351 [patent_doc_number] => 08906729 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-09 [patent_title] => 'Method of manufacturing a device with a cavity' [patent_app_type] => utility [patent_app_number] => 13/673494 [patent_app_country] => US [patent_app_date] => 2012-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 37 [patent_no_of_words] => 7846 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13673494 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/673494
Method of manufacturing a device with a cavity Nov 8, 2012 Issued
Array ( [id] => 8582821 [patent_doc_number] => 20130001642 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'METHOD INCLUDING PRODUCING A MONOCRYSTALLINE LAYER' [patent_app_type] => utility [patent_app_number] => 13/610206 [patent_app_country] => US [patent_app_date] => 2012-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2689 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13610206 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/610206
Monocrystalline substrate including lattice matching atoms in a near surface region and a monocrystalline layer disposed on the substrate Sep 10, 2012 Issued
Array ( [id] => 9086244 [patent_doc_number] => 08557671 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-15 [patent_title] => 'Method for forming a transient voltage suppressor having symmetrical breakdown voltages' [patent_app_type] => utility [patent_app_number] => 13/604834 [patent_app_country] => US [patent_app_date] => 2012-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 26 [patent_no_of_words] => 6343 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13604834 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/604834
Method for forming a transient voltage suppressor having symmetrical breakdown voltages Sep 5, 2012 Issued
Array ( [id] => 9977412 [patent_doc_number] => 09023724 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-05 [patent_title] => 'Method of manufacturing semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 13/601785 [patent_app_country] => US [patent_app_date] => 2012-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2304 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13601785 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/601785
Method of manufacturing semiconductor memory device Aug 30, 2012 Issued
Array ( [id] => 8888547 [patent_doc_number] => 20130161731 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-27 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/601355 [patent_app_country] => US [patent_app_date] => 2012-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10630 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13601355 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/601355
Three-dimensional semiconductor device Aug 30, 2012 Issued
Array ( [id] => 10837890 [patent_doc_number] => 08865562 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-21 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/601676 [patent_app_country] => US [patent_app_date] => 2012-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 6189 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13601676 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/601676
Method of manufacturing semiconductor device Aug 30, 2012 Issued
Array ( [id] => 8519778 [patent_doc_number] => 20120319186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-20 [patent_title] => 'MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/597141 [patent_app_country] => US [patent_app_date] => 2012-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3053 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13597141 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/597141
Memory device and method for fabricating the same Aug 27, 2012 Issued
Array ( [id] => 8563635 [patent_doc_number] => 20120326206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-27 [patent_title] => 'DEVICES WITH ZENER TRIGGERED ESD PROTECTION' [patent_app_type] => utility [patent_app_number] => 13/593608 [patent_app_country] => US [patent_app_date] => 2012-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8004 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13593608 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/593608
Devices with zener triggered ESD protection Aug 23, 2012 Issued
Array ( [id] => 8994951 [patent_doc_number] => 08518835 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-27 [patent_title] => 'Methods of utilizing block copolymers to form patterns' [patent_app_type] => utility [patent_app_number] => 13/589892 [patent_app_country] => US [patent_app_date] => 2012-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 35 [patent_no_of_words] => 15940 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13589892 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/589892
Methods of utilizing block copolymers to form patterns Aug 19, 2012 Issued
Array ( [id] => 8932560 [patent_doc_number] => 08492259 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-23 [patent_title] => 'Method of forming metal gate structure' [patent_app_type] => utility [patent_app_number] => 13/586874 [patent_app_country] => US [patent_app_date] => 2012-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4807 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13586874 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/586874
Method of forming metal gate structure Aug 15, 2012 Issued
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