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Steven A. Friday

Examiner (ID: 7266, Phone: (571)270-7932 , Office: P/1756 )

Most Active Art Unit
1756
Art Unit(s)
1724, 1795, 1756
Total Applications
364
Issued Applications
170
Pending Applications
2
Abandoned Applications
193

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5044121 [patent_doc_number] => 20070262792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-15 [patent_title] => 'Reduced glitch dynamic logic circuit and method of synthesis for complementary oxide semiconductor (CMOS) and strained/unstrained silicon-on-insulator (SOI)' [patent_app_type] => utility [patent_app_number] => 10/638756 [patent_app_country] => US [patent_app_date] => 2003-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9657 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0262/20070262792.pdf [firstpage_image] =>[orig_patent_app_number] => 10638756 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/638756
Reduced glitch dynamic logic circuit and method of synthesis for complementary oxide semiconductor (CMOS) and strained/unstrained silicon-on-insulator (SOI) Aug 10, 2003 Issued
Array ( [id] => 7158280 [patent_doc_number] => 20050027505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-03 [patent_title] => 'Configuration of reconfigurable interconnect portions' [patent_app_type] => utility [patent_app_number] => 10/631824 [patent_app_country] => US [patent_app_date] => 2003-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7897 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20050027505.pdf [firstpage_image] =>[orig_patent_app_number] => 10631824 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/631824
Configuration of reconfigurable interconnect portions Jul 31, 2003 Issued
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