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[patent_title] => 'Reduced glitch dynamic logic circuit and method of synthesis for complementary oxide semiconductor (CMOS) and strained/unstrained silicon-on-insulator (SOI)'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/638756 | Reduced glitch dynamic logic circuit and method of synthesis for complementary oxide semiconductor (CMOS) and strained/unstrained silicon-on-insulator (SOI) | Aug 10, 2003 | Issued |