Search

Steven A. Friday

Examiner (ID: 7266, Phone: (571)270-7932 , Office: P/1756 )

Most Active Art Unit
1756
Art Unit(s)
1724, 1795, 1756
Total Applications
364
Issued Applications
170
Pending Applications
2
Abandoned Applications
193

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4548861 [patent_doc_number] => 07876630 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-01-25 [patent_title] => 'Postamble timing for DDR memories' [patent_app_type] => utility [patent_app_number] => 11/935405 [patent_app_country] => US [patent_app_date] => 2007-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 5725 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/876/07876630.pdf [firstpage_image] =>[orig_patent_app_number] => 11935405 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/935405
Postamble timing for DDR memories Nov 5, 2007 Issued
Array ( [id] => 5262766 [patent_doc_number] => 20090115451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-07 [patent_title] => 'CONFIGURABLE AND REUSABLE NAND SYSTEM' [patent_app_type] => utility [patent_app_number] => 11/934790 [patent_app_country] => US [patent_app_date] => 2007-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2119 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20090115451.pdf [firstpage_image] =>[orig_patent_app_number] => 11934790 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/934790
CONFIGURABLE AND REUSABLE NAND SYSTEM Nov 4, 2007 Abandoned
Array ( [id] => 212039 [patent_doc_number] => 07622946 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-24 [patent_title] => 'Design structure for an automatic driver/transmission line/receiver impedance matching circuitry' [patent_app_type] => utility [patent_app_number] => 11/934825 [patent_app_country] => US [patent_app_date] => 2007-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5526 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/622/07622946.pdf [firstpage_image] =>[orig_patent_app_number] => 11934825 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/934825
Design structure for an automatic driver/transmission line/receiver impedance matching circuitry Nov 4, 2007 Issued
Array ( [id] => 169957 [patent_doc_number] => 07667489 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-02-23 [patent_title] => 'Power-on reset circuit for a voltage regulator having multiple power supply voltages' [patent_app_type] => utility [patent_app_number] => 11/977831 [patent_app_country] => US [patent_app_date] => 2007-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 15085 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/667/07667489.pdf [firstpage_image] =>[orig_patent_app_number] => 11977831 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/977831
Power-on reset circuit for a voltage regulator having multiple power supply voltages Oct 25, 2007 Issued
Array ( [id] => 5583523 [patent_doc_number] => 20090102725 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-23 [patent_title] => 'ENGAGING STRUCTURE WITH RADIATION FUNCTION IN AN OPENABLE COVER OF PORTABLE ELECTRONIC EQUIPMENT' [patent_app_type] => utility [patent_app_number] => 11/877204 [patent_app_country] => US [patent_app_date] => 2007-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 1245 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20090102725.pdf [firstpage_image] =>[orig_patent_app_number] => 11877204 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/877204
ENGAGING STRUCTURE WITH RADIATION FUNCTION IN AN OPENABLE COVER OF PORTABLE ELECTRONIC EQUIPMENT Oct 22, 2007 Abandoned
Array ( [id] => 4750955 [patent_doc_number] => 20080159026 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'MEMORY SYSTEMS, ON-DIE TERMINATION (ODT) CIRCUITS, AND METHOD OF ODT CONTROL' [patent_app_type] => utility [patent_app_number] => 11/873461 [patent_app_country] => US [patent_app_date] => 2007-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 6188 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20080159026.pdf [firstpage_image] =>[orig_patent_app_number] => 11873461 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/873461
Memory systems, on-die termination (ODT) circuits, and method of ODT control Oct 16, 2007 Issued
Array ( [id] => 5283025 [patent_doc_number] => 20090096699 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-16 [patent_title] => 'COMPACT 3-PORT ORTHOGONALLY POLARIZED MIMO ANTENNAS' [patent_app_type] => utility [patent_app_number] => 11/873071 [patent_app_country] => US [patent_app_date] => 2007-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12873 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20090096699.pdf [firstpage_image] =>[orig_patent_app_number] => 11873071 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/873071
Compact 3-port orthogonally polarized MIMO antennas Oct 15, 2007 Issued
Array ( [id] => 4913707 [patent_doc_number] => 20080094306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-24 [patent_title] => 'Wireless Network Card Antenna Position Structure' [patent_app_type] => utility [patent_app_number] => 11/867224 [patent_app_country] => US [patent_app_date] => 2007-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1564 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20080094306.pdf [firstpage_image] =>[orig_patent_app_number] => 11867224 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/867224
Wireless Network Card Antenna Position Structure Oct 3, 2007 Abandoned
Array ( [id] => 5426502 [patent_doc_number] => 20090085812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-02 [patent_title] => 'MOBILE WIRELESS COMMUNICATIONS DEVICE ANTENNA ASSEMBLY WITH ANTENNA ELEMENT AND FLOATING DIRECTOR ELEMENT ON FLEXIBLE SUBSTRATE AND RELATED METHODS' [patent_app_type] => utility [patent_app_number] => 11/863324 [patent_app_country] => US [patent_app_date] => 2007-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4721 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20090085812.pdf [firstpage_image] =>[orig_patent_app_number] => 11863324 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/863324
Mobile wireless communications device antenna assembly with antenna element and floating director element on flexible substrate and related methods Sep 27, 2007 Issued
Array ( [id] => 4579419 [patent_doc_number] => 07830315 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-09 [patent_title] => 'Antenna apparatus and radio communicating apparatus' [patent_app_type] => utility [patent_app_number] => 11/864462 [patent_app_country] => US [patent_app_date] => 2007-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 51 [patent_no_of_words] => 10358 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/830/07830315.pdf [firstpage_image] =>[orig_patent_app_number] => 11864462 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/864462
Antenna apparatus and radio communicating apparatus Sep 27, 2007 Issued
Array ( [id] => 186295 [patent_doc_number] => 07646220 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-12 [patent_title] => 'Reduced voltage subLVDS receiver' [patent_app_type] => utility [patent_app_number] => 11/904652 [patent_app_country] => US [patent_app_date] => 2007-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4726 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/646/07646220.pdf [firstpage_image] =>[orig_patent_app_number] => 11904652 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/904652
Reduced voltage subLVDS receiver Sep 26, 2007 Issued
Array ( [id] => 4877200 [patent_doc_number] => 20080150583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'BUFFER CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/853003 [patent_app_country] => US [patent_app_date] => 2007-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4280 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20080150583.pdf [firstpage_image] =>[orig_patent_app_number] => 11853003 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/853003
Buffer circuit Sep 9, 2007 Issued
Array ( [id] => 304110 [patent_doc_number] => 07535251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-19 [patent_title] => 'Semiconductor device and impedance adjusting method thereof' [patent_app_type] => utility [patent_app_number] => 11/852032 [patent_app_country] => US [patent_app_date] => 2007-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 20692 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 318 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/535/07535251.pdf [firstpage_image] =>[orig_patent_app_number] => 11852032 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/852032
Semiconductor device and impedance adjusting method thereof Sep 6, 2007 Issued
Array ( [id] => 4743739 [patent_doc_number] => 20080088340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'MILLER CAPACITANCE TOLERANT BUFFER ELEMENT' [patent_app_type] => utility [patent_app_number] => 11/851381 [patent_app_country] => US [patent_app_date] => 2007-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3402 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20080088340.pdf [firstpage_image] =>[orig_patent_app_number] => 11851381 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/851381
Miller capacitance tolerant buffer element Sep 5, 2007 Issued
Array ( [id] => 197875 [patent_doc_number] => 07639046 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-29 [patent_title] => 'Method to reduce power consumption within a clock gated synchronous circuit and clock gated synchronous circuit' [patent_app_type] => utility [patent_app_number] => 11/850736 [patent_app_country] => US [patent_app_date] => 2007-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4241 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 287 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/639/07639046.pdf [firstpage_image] =>[orig_patent_app_number] => 11850736 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/850736
Method to reduce power consumption within a clock gated synchronous circuit and clock gated synchronous circuit Sep 5, 2007 Issued
Array ( [id] => 143083 [patent_doc_number] => 07688115 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-30 [patent_title] => 'CMOS output driver' [patent_app_type] => utility [patent_app_number] => 11/849655 [patent_app_country] => US [patent_app_date] => 2007-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1742 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/688/07688115.pdf [firstpage_image] =>[orig_patent_app_number] => 11849655 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/849655
CMOS output driver Sep 3, 2007 Issued
Array ( [id] => 83249 [patent_doc_number] => 07746137 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-29 [patent_title] => 'Sequential circuit element including a single clocked transistor' [patent_app_type] => utility [patent_app_number] => 11/845950 [patent_app_country] => US [patent_app_date] => 2007-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7006 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/746/07746137.pdf [firstpage_image] =>[orig_patent_app_number] => 11845950 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/845950
Sequential circuit element including a single clocked transistor Aug 27, 2007 Issued
Array ( [id] => 5334922 [patent_doc_number] => 20090051386 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-26 [patent_title] => ' Integrate Circuit Chip with Magnetic Devices' [patent_app_type] => utility [patent_app_number] => 11/841193 [patent_app_country] => US [patent_app_date] => 2007-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1664 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20090051386.pdf [firstpage_image] =>[orig_patent_app_number] => 11841193 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/841193
Integrate circuit chip with magnetic devices Aug 19, 2007 Issued
Array ( [id] => 4731744 [patent_doc_number] => 20080048722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'DRIVE CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/840687 [patent_app_country] => US [patent_app_date] => 2007-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9422 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20080048722.pdf [firstpage_image] =>[orig_patent_app_number] => 11840687 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/840687
Drive circuit Aug 16, 2007 Issued
Array ( [id] => 229402 [patent_doc_number] => 07602217 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-13 [patent_title] => 'Level shifter circuit with pre-charge/pre-discharge' [patent_app_type] => utility [patent_app_number] => 11/839611 [patent_app_country] => US [patent_app_date] => 2007-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2723 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/602/07602217.pdf [firstpage_image] =>[orig_patent_app_number] => 11839611 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/839611
Level shifter circuit with pre-charge/pre-discharge Aug 15, 2007 Issued
Menu