
Steven A. Friday
Examiner (ID: 7266, Phone: (571)270-7932 , Office: P/1756 )
| Most Active Art Unit | 1756 |
| Art Unit(s) | 1724, 1795, 1756 |
| Total Applications | 364 |
| Issued Applications | 170 |
| Pending Applications | 2 |
| Abandoned Applications | 193 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4548861
[patent_doc_number] => 07876630
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2011-01-25
[patent_title] => 'Postamble timing for DDR memories'
[patent_app_type] => utility
[patent_app_number] => 11/935405
[patent_app_country] => US
[patent_app_date] => 2007-11-06
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/876/07876630.pdf
[firstpage_image] =>[orig_patent_app_number] => 11935405
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/935405 | Postamble timing for DDR memories | Nov 5, 2007 | Issued |
Array
(
[id] => 5262766
[patent_doc_number] => 20090115451
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-05-07
[patent_title] => 'CONFIGURABLE AND REUSABLE NAND SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 11/934790
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/934790 | CONFIGURABLE AND REUSABLE NAND SYSTEM | Nov 4, 2007 | Abandoned |
Array
(
[id] => 212039
[patent_doc_number] => 07622946
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-11-24
[patent_title] => 'Design structure for an automatic driver/transmission line/receiver impedance matching circuitry'
[patent_app_type] => utility
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[firstpage_image] =>[orig_patent_app_number] => 11934825
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/934825 | Design structure for an automatic driver/transmission line/receiver impedance matching circuitry | Nov 4, 2007 | Issued |
Array
(
[id] => 169957
[patent_doc_number] => 07667489
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-02-23
[patent_title] => 'Power-on reset circuit for a voltage regulator having multiple power supply voltages'
[patent_app_type] => utility
[patent_app_number] => 11/977831
[patent_app_country] => US
[patent_app_date] => 2007-10-26
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[firstpage_image] =>[orig_patent_app_number] => 11977831
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/977831 | Power-on reset circuit for a voltage regulator having multiple power supply voltages | Oct 25, 2007 | Issued |
Array
(
[id] => 5583523
[patent_doc_number] => 20090102725
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-23
[patent_title] => 'ENGAGING STRUCTURE WITH RADIATION FUNCTION IN AN OPENABLE COVER OF PORTABLE ELECTRONIC EQUIPMENT'
[patent_app_type] => utility
[patent_app_number] => 11/877204
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Array
(
[id] => 4750955
[patent_doc_number] => 20080159026
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[patent_kind] => A1
[patent_issue_date] => 2008-07-03
[patent_title] => 'MEMORY SYSTEMS, ON-DIE TERMINATION (ODT) CIRCUITS, AND METHOD OF ODT CONTROL'
[patent_app_type] => utility
[patent_app_number] => 11/873461
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 11873461
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/873461 | Memory systems, on-die termination (ODT) circuits, and method of ODT control | Oct 16, 2007 | Issued |
Array
(
[id] => 5283025
[patent_doc_number] => 20090096699
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-16
[patent_title] => 'COMPACT 3-PORT ORTHOGONALLY POLARIZED MIMO ANTENNAS'
[patent_app_type] => utility
[patent_app_number] => 11/873071
[patent_app_country] => US
[patent_app_date] => 2007-10-16
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0096/20090096699.pdf
[firstpage_image] =>[orig_patent_app_number] => 11873071
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/873071 | Compact 3-port orthogonally polarized MIMO antennas | Oct 15, 2007 | Issued |
Array
(
[id] => 4913707
[patent_doc_number] => 20080094306
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-04-24
[patent_title] => 'Wireless Network Card Antenna Position Structure'
[patent_app_type] => utility
[patent_app_number] => 11/867224
[patent_app_country] => US
[patent_app_date] => 2007-10-04
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 11867224
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/867224 | Wireless Network Card Antenna Position Structure | Oct 3, 2007 | Abandoned |
Array
(
[id] => 5426502
[patent_doc_number] => 20090085812
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-02
[patent_title] => 'MOBILE WIRELESS COMMUNICATIONS DEVICE ANTENNA ASSEMBLY WITH ANTENNA ELEMENT AND FLOATING DIRECTOR ELEMENT ON FLEXIBLE SUBSTRATE AND RELATED METHODS'
[patent_app_type] => utility
[patent_app_number] => 11/863324
[patent_app_country] => US
[patent_app_date] => 2007-09-28
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0085/20090085812.pdf
[firstpage_image] =>[orig_patent_app_number] => 11863324
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/863324 | Mobile wireless communications device antenna assembly with antenna element and floating director element on flexible substrate and related methods | Sep 27, 2007 | Issued |
Array
(
[id] => 4579419
[patent_doc_number] => 07830315
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-11-09
[patent_title] => 'Antenna apparatus and radio communicating apparatus'
[patent_app_type] => utility
[patent_app_number] => 11/864462
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/864462 | Antenna apparatus and radio communicating apparatus | Sep 27, 2007 | Issued |
Array
(
[id] => 186295
[patent_doc_number] => 07646220
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-01-12
[patent_title] => 'Reduced voltage subLVDS receiver'
[patent_app_type] => utility
[patent_app_number] => 11/904652
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/904652 | Reduced voltage subLVDS receiver | Sep 26, 2007 | Issued |
Array
(
[id] => 4877200
[patent_doc_number] => 20080150583
[patent_country] => US
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[patent_title] => 'BUFFER CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 11/853003
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/853003 | Buffer circuit | Sep 9, 2007 | Issued |
Array
(
[id] => 304110
[patent_doc_number] => 07535251
[patent_country] => US
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[patent_issue_date] => 2009-05-19
[patent_title] => 'Semiconductor device and impedance adjusting method thereof'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/852032 | Semiconductor device and impedance adjusting method thereof | Sep 6, 2007 | Issued |
Array
(
[id] => 4743739
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[patent_country] => US
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[patent_issue_date] => 2008-04-17
[patent_title] => 'MILLER CAPACITANCE TOLERANT BUFFER ELEMENT'
[patent_app_type] => utility
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Array
(
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[patent_title] => 'Method to reduce power consumption within a clock gated synchronous circuit and clock gated synchronous circuit'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/850736 | Method to reduce power consumption within a clock gated synchronous circuit and clock gated synchronous circuit | Sep 5, 2007 | Issued |
Array
(
[id] => 143083
[patent_doc_number] => 07688115
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[patent_title] => 'CMOS output driver'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/849655 | CMOS output driver | Sep 3, 2007 | Issued |
Array
(
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[patent_title] => 'Sequential circuit element including a single clocked transistor'
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Array
(
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[patent_title] => ' Integrate Circuit Chip with Magnetic Devices'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/841193 | Integrate circuit chip with magnetic devices | Aug 19, 2007 | Issued |
Array
(
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/839611 | Level shifter circuit with pre-charge/pre-discharge | Aug 15, 2007 | Issued |