
Steven A. Friday
Examiner (ID: 7266, Phone: (571)270-7932 , Office: P/1756 )
| Most Active Art Unit | 1756 |
| Art Unit(s) | 1724, 1795, 1756 |
| Total Applications | 364 |
| Issued Applications | 170 |
| Pending Applications | 2 |
| Abandoned Applications | 193 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5214109
[patent_doc_number] => 20070103189
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-05-10
[patent_title] => 'Semiconductor device, test system and method of testing on die termination circuit'
[patent_app_type] => utility
[patent_app_number] => 11/585615
[patent_app_country] => US
[patent_app_date] => 2006-10-24
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[pdf_file] => publications/A1/0103/20070103189.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/585615 | Semiconductor device, test system and method of testing on die termination circuit | Oct 23, 2006 | Issued |
Array
(
[id] => 4902171
[patent_doc_number] => 20080111584
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-05-15
[patent_title] => 'Longitudinal balance calibration for a subscriber line interface circuit'
[patent_app_type] => utility
[patent_app_number] => 11/586425
[patent_app_country] => US
[patent_app_date] => 2006-10-23
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/586425 | Longitudinal balance calibration for a subscriber line interface circuit | Oct 22, 2006 | Issued |
Array
(
[id] => 5214120
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[patent_kind] => A1
[patent_issue_date] => 2007-05-10
[patent_title] => 'Buffer circuit and use thereof'
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[patent_app_number] => 11/584242
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[firstpage_image] =>[orig_patent_app_number] => 11584242
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/584242 | Buffer circuit and use thereof | Oct 19, 2006 | Abandoned |
Array
(
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[patent_doc_number] => 07812633
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[patent_issue_date] => 2010-10-12
[patent_title] => 'Apparatus and method for the arithmetic over-ride of look up table outputs in a programmable logic device'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/584308 | Apparatus and method for the arithmetic over-ride of look up table outputs in a programmable logic device | Oct 19, 2006 | Issued |
Array
(
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[patent_doc_number] => 07589560
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[patent_issue_date] => 2009-09-15
[patent_title] => 'Apparatus for configuring I/O signal levels of interfacing logic circuits'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/583322 | Apparatus for configuring I/O signal levels of interfacing logic circuits | Oct 18, 2006 | Issued |
Array
(
[id] => 5214108
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[patent_issue_date] => 2007-05-10
[patent_title] => 'Semiconductor memory chip with on-die termination function'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/582981 | Semiconductor memory chip with on-die termination function | Oct 18, 2006 | Issued |
Array
(
[id] => 5020042
[patent_doc_number] => 20070146008
[patent_country] => US
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[patent_issue_date] => 2007-06-28
[patent_title] => 'Semiconductor circuit comprising vertical transistor'
[patent_app_type] => utility
[patent_app_number] => 11/581390
[patent_app_country] => US
[patent_app_date] => 2006-10-17
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[firstpage_image] =>[orig_patent_app_number] => 11581390
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/581390 | Semiconductor circuit comprising vertical transistor | Oct 16, 2006 | Abandoned |
Array
(
[id] => 278532
[patent_doc_number] => 07557610
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-07-07
[patent_title] => 'Columnar floorplan'
[patent_app_type] => utility
[patent_app_number] => 11/581914
[patent_app_country] => US
[patent_app_date] => 2006-10-17
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/557/07557610.pdf
[firstpage_image] =>[orig_patent_app_number] => 11581914
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/581914 | Columnar floorplan | Oct 16, 2006 | Issued |
Array
(
[id] => 103470
[patent_doc_number] => 07728624
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[patent_issue_date] => 2010-06-01
[patent_title] => 'Circuit architecture for an integrated circuit'
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[patent_app_number] => 11/546011
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[firstpage_image] =>[orig_patent_app_number] => 11546011
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/546011 | Circuit architecture for an integrated circuit | Oct 9, 2006 | Issued |
Array
(
[id] => 163582
[patent_doc_number] => 07671624
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-03-02
[patent_title] => 'Method to reduce configuration solution using masked-ROM'
[patent_app_type] => utility
[patent_app_number] => 11/546057
[patent_app_country] => US
[patent_app_date] => 2006-10-10
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[pdf_file] => patents/07/671/07671624.pdf
[firstpage_image] =>[orig_patent_app_number] => 11546057
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/546057 | Method to reduce configuration solution using masked-ROM | Oct 9, 2006 | Issued |
Array
(
[id] => 4444232
[patent_doc_number] => 07928764
[patent_country] => US
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[patent_issue_date] => 2011-04-19
[patent_title] => 'Programmable interconnect network for logic array'
[patent_app_type] => utility
[patent_app_number] => 12/375560
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[firstpage_image] =>[orig_patent_app_number] => 12375560
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/375560 | Programmable interconnect network for logic array | Aug 30, 2006 | Issued |
Array
(
[id] => 93751
[patent_doc_number] => 07737804
[patent_country] => US
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[patent_title] => 'Support for acoustic resonator and corresponding integrated circuit'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/511082 | Support for acoustic resonator and corresponding integrated circuit | Aug 27, 2006 | Issued |
Array
(
[id] => 4731747
[patent_doc_number] => 20080048725
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-02-28
[patent_title] => 'Domino Circuit with Master and Slave (DUAL) Pull Down Paths'
[patent_app_type] => utility
[patent_app_number] => 11/466113
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/466113 | Domino Circuit with Master and Slave (DUAL) Pull Down Paths | Aug 21, 2006 | Abandoned |
Array
(
[id] => 4997999
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[patent_title] => 'Acoustic surface wave filter module and method of manufacturing the same'
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Array
(
[id] => 4769280
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Array
(
[id] => 4578401
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/493844 | Controlling signal levels on a signal line within an integrated circuit | Jul 26, 2006 | Issued |
Array
(
[id] => 304120
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[patent_title] => 'Logic circuit'
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Array
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/490151 | Common input/output terminal control circuit | Jul 20, 2006 | Issued |
Array
(
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[patent_title] => 'PVT variation detection and compensation circuit'
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[firstpage_image] =>[orig_patent_app_number] => 11490441
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/490441 | PVT variation detection and compensation circuit | Jul 19, 2006 | Issued |