Search

Steven A. Friday

Examiner (ID: 7266, Phone: (571)270-7932 , Office: P/1756 )

Most Active Art Unit
1756
Art Unit(s)
1724, 1795, 1756
Total Applications
364
Issued Applications
170
Pending Applications
2
Abandoned Applications
193

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5214109 [patent_doc_number] => 20070103189 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-10 [patent_title] => 'Semiconductor device, test system and method of testing on die termination circuit' [patent_app_type] => utility [patent_app_number] => 11/585615 [patent_app_country] => US [patent_app_date] => 2006-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5827 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20070103189.pdf [firstpage_image] =>[orig_patent_app_number] => 11585615 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/585615
Semiconductor device, test system and method of testing on die termination circuit Oct 23, 2006 Issued
Array ( [id] => 4902171 [patent_doc_number] => 20080111584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-15 [patent_title] => 'Longitudinal balance calibration for a subscriber line interface circuit' [patent_app_type] => utility [patent_app_number] => 11/586425 [patent_app_country] => US [patent_app_date] => 2006-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 6569 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20080111584.pdf [firstpage_image] =>[orig_patent_app_number] => 11586425 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/586425
Longitudinal balance calibration for a subscriber line interface circuit Oct 22, 2006 Issued
Array ( [id] => 5214120 [patent_doc_number] => 20070103200 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-10 [patent_title] => 'Buffer circuit and use thereof' [patent_app_type] => utility [patent_app_number] => 11/584242 [patent_app_country] => US [patent_app_date] => 2006-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3735 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20070103200.pdf [firstpage_image] =>[orig_patent_app_number] => 11584242 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/584242
Buffer circuit and use thereof Oct 19, 2006 Abandoned
Array ( [id] => 5888 [patent_doc_number] => 07812633 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-10-12 [patent_title] => 'Apparatus and method for the arithmetic over-ride of look up table outputs in a programmable logic device' [patent_app_type] => utility [patent_app_number] => 11/584308 [patent_app_country] => US [patent_app_date] => 2006-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3452 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/812/07812633.pdf [firstpage_image] =>[orig_patent_app_number] => 11584308 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/584308
Apparatus and method for the arithmetic over-ride of look up table outputs in a programmable logic device Oct 19, 2006 Issued
Array ( [id] => 243823 [patent_doc_number] => 07589560 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-15 [patent_title] => 'Apparatus for configuring I/O signal levels of interfacing logic circuits' [patent_app_type] => utility [patent_app_number] => 11/583322 [patent_app_country] => US [patent_app_date] => 2006-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2245 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/589/07589560.pdf [firstpage_image] =>[orig_patent_app_number] => 11583322 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/583322
Apparatus for configuring I/O signal levels of interfacing logic circuits Oct 18, 2006 Issued
Array ( [id] => 5214108 [patent_doc_number] => 20070103188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-10 [patent_title] => 'Semiconductor memory chip with on-die termination function' [patent_app_type] => utility [patent_app_number] => 11/582981 [patent_app_country] => US [patent_app_date] => 2006-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2744 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20070103188.pdf [firstpage_image] =>[orig_patent_app_number] => 11582981 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/582981
Semiconductor memory chip with on-die termination function Oct 18, 2006 Issued
Array ( [id] => 5020042 [patent_doc_number] => 20070146008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'Semiconductor circuit comprising vertical transistor' [patent_app_type] => utility [patent_app_number] => 11/581390 [patent_app_country] => US [patent_app_date] => 2006-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5231 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20070146008.pdf [firstpage_image] =>[orig_patent_app_number] => 11581390 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/581390
Semiconductor circuit comprising vertical transistor Oct 16, 2006 Abandoned
Array ( [id] => 278532 [patent_doc_number] => 07557610 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-07 [patent_title] => 'Columnar floorplan' [patent_app_type] => utility [patent_app_number] => 11/581914 [patent_app_country] => US [patent_app_date] => 2006-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 7169 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/557/07557610.pdf [firstpage_image] =>[orig_patent_app_number] => 11581914 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/581914
Columnar floorplan Oct 16, 2006 Issued
Array ( [id] => 103470 [patent_doc_number] => 07728624 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-01 [patent_title] => 'Circuit architecture for an integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/546011 [patent_app_country] => US [patent_app_date] => 2006-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3715 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/728/07728624.pdf [firstpage_image] =>[orig_patent_app_number] => 11546011 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/546011
Circuit architecture for an integrated circuit Oct 9, 2006 Issued
Array ( [id] => 163582 [patent_doc_number] => 07671624 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-03-02 [patent_title] => 'Method to reduce configuration solution using masked-ROM' [patent_app_type] => utility [patent_app_number] => 11/546057 [patent_app_country] => US [patent_app_date] => 2006-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5672 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/671/07671624.pdf [firstpage_image] =>[orig_patent_app_number] => 11546057 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/546057
Method to reduce configuration solution using masked-ROM Oct 9, 2006 Issued
Array ( [id] => 4444232 [patent_doc_number] => 07928764 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-19 [patent_title] => 'Programmable interconnect network for logic array' [patent_app_type] => utility [patent_app_number] => 12/375560 [patent_app_country] => US [patent_app_date] => 2006-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3817 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/928/07928764.pdf [firstpage_image] =>[orig_patent_app_number] => 12375560 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/375560
Programmable interconnect network for logic array Aug 30, 2006 Issued
Array ( [id] => 93751 [patent_doc_number] => 07737804 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-15 [patent_title] => 'Support for acoustic resonator and corresponding integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/511082 [patent_app_country] => US [patent_app_date] => 2006-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 3460 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/737/07737804.pdf [firstpage_image] =>[orig_patent_app_number] => 11511082 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/511082
Support for acoustic resonator and corresponding integrated circuit Aug 27, 2006 Issued
Array ( [id] => 4731747 [patent_doc_number] => 20080048725 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'Domino Circuit with Master and Slave (DUAL) Pull Down Paths' [patent_app_type] => utility [patent_app_number] => 11/466113 [patent_app_country] => US [patent_app_date] => 2006-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3287 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20080048725.pdf [firstpage_image] =>[orig_patent_app_number] => 11466113 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/466113
Domino Circuit with Master and Slave (DUAL) Pull Down Paths Aug 21, 2006 Abandoned
Array ( [id] => 4997999 [patent_doc_number] => 20070040633 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'Acoustic surface wave filter module and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/504787 [patent_app_country] => US [patent_app_date] => 2006-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4218 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20070040633.pdf [firstpage_image] =>[orig_patent_app_number] => 11504787 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/504787
Acoustic surface wave filter module and method of manufacturing the same Aug 14, 2006 Abandoned
Array ( [id] => 4769280 [patent_doc_number] => 20080054938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'Microcontroller with low noise peripheral' [patent_app_type] => utility [patent_app_number] => 11/460854 [patent_app_country] => US [patent_app_date] => 2006-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3260 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20080054938.pdf [firstpage_image] =>[orig_patent_app_number] => 11460854 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/460854
Microcontroller with low noise peripheral Jul 27, 2006 Abandoned
Array ( [id] => 4578401 [patent_doc_number] => 07830176 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-09 [patent_title] => 'Controlling signal levels on a signal line within an integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/493844 [patent_app_country] => US [patent_app_date] => 2006-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2728 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/830/07830176.pdf [firstpage_image] =>[orig_patent_app_number] => 11493844 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/493844
Controlling signal levels on a signal line within an integrated circuit Jul 26, 2006 Issued
Array ( [id] => 304120 [patent_doc_number] => 07535261 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-19 [patent_title] => 'Logic circuit' [patent_app_type] => utility [patent_app_number] => 11/492894 [patent_app_country] => US [patent_app_date] => 2006-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 8611 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/535/07535261.pdf [firstpage_image] =>[orig_patent_app_number] => 11492894 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/492894
Logic circuit Jul 25, 2006 Issued
Array ( [id] => 289470 [patent_doc_number] => 07548087 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-16 [patent_title] => 'Impedance adjusting circuit and impedance adjusting method' [patent_app_type] => utility [patent_app_number] => 11/492035 [patent_app_country] => US [patent_app_date] => 2006-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 5260 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/548/07548087.pdf [firstpage_image] =>[orig_patent_app_number] => 11492035 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/492035
Impedance adjusting circuit and impedance adjusting method Jul 24, 2006 Issued
Array ( [id] => 583824 [patent_doc_number] => 07456657 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-25 [patent_title] => 'Common input/output terminal control circuit' [patent_app_type] => utility [patent_app_number] => 11/490151 [patent_app_country] => US [patent_app_date] => 2006-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6127 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/456/07456657.pdf [firstpage_image] =>[orig_patent_app_number] => 11490151 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/490151
Common input/output terminal control circuit Jul 20, 2006 Issued
Array ( [id] => 5240373 [patent_doc_number] => 20070018864 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-25 [patent_title] => 'PVT variation detection and compensation circuit' [patent_app_type] => utility [patent_app_number] => 11/490441 [patent_app_country] => US [patent_app_date] => 2006-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3488 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20070018864.pdf [firstpage_image] =>[orig_patent_app_number] => 11490441 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/490441
PVT variation detection and compensation circuit Jul 19, 2006 Issued
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