Steven A. Friday

Array ( [id] => 5083353 [patent_doc_number] => 20070273404 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-29 [patent_title] => 'Mixed voltage input/output buffer having low-voltage design' [patent_app_type] => utility [patent_app_number] => 11/489325 [patent_app_country] => US [patent_app_date] => 2006-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3149 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0273/20070273404.pdf [firstpage_image] =>[orig_patent_app_number] => 11489325 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 594155 [patent_doc_number] => 07436208 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-10-14 [patent_title] => 'Carry circuit with power-save mode' [patent_app_type] => utility [patent_app_number] => 11/487916 [patent_app_country] => US [patent_app_date] => 2006-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5568 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/436/07436208.pdf [firstpage_image] =>[orig_patent_app_number] => 11487916 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 217726 [patent_doc_number] => 07612638 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-03 [patent_title] => 'Waveguides in integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/486903 [patent_app_country] => US [patent_app_date] => 2006-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 1851 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/612/07612638.pdf [firstpage_image] =>[orig_patent_app_number] => 11486903 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 814153 [patent_doc_number] => 07414429 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-08-19 [patent_title] => 'Integration of high-speed serial interface circuitry into programmable logic device architectures' [patent_app_type] => utility [patent_app_number] => 11/486867 [patent_app_country] => US [patent_app_date] => 2006-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 5092 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/414/07414429.pdf [firstpage_image] =>[orig_patent_app_number] => 11486867 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4975211 [patent_doc_number] => 20070216441 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-20 [patent_title] => 'Terminating resistance adjusting method, semiconductor integrated circuit and semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/485396 [patent_app_country] => US [patent_app_date] => 2006-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 46 [patent_no_of_words] => 10158 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20070216441.pdf [firstpage_image] =>[orig_patent_app_number] => 11485396 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 124544 [patent_doc_number] => 07705628 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-04-27 [patent_title] => 'Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers' [patent_app_type] => utility [patent_app_number] => 11/486164 [patent_app_country] => US [patent_app_date] => 2006-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 5793 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/705/07705628.pdf [firstpage_image] =>[orig_patent_app_number] => 11486164 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 186272 [patent_doc_number] => 07646209 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-12 [patent_title] => 'Semiconductor integrated circuit and method of production of same' [patent_app_type] => utility [patent_app_number] => 11/482808 [patent_app_country] => US [patent_app_date] => 2006-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 67 [patent_no_of_words] => 36953 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/646/07646209.pdf [firstpage_image] =>[orig_patent_app_number] => 11482808 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5008609 [patent_doc_number] => 20070279086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-06 [patent_title] => 'ANTIFUSE PROGRAMMING CIRCUIT WITH SNAPBACK SELECT TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 11/421614 [patent_app_country] => US [patent_app_date] => 2006-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3969 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0279/20070279086.pdf [firstpage_image] =>[orig_patent_app_number] => 11421614 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5240203 [patent_doc_number] => 20070018694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-25 [patent_title] => 'HIGH-SPEED CML CIRCUIT DESIGN' [patent_app_type] => utility [patent_app_number] => 11/421675 [patent_app_country] => US [patent_app_date] => 2006-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4278 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20070018694.pdf [firstpage_image] =>[orig_patent_app_number] => 11421675 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 798288 [patent_doc_number] => 07427878 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-23 [patent_title] => 'Low-voltage differential signal driver for high-speed digital transmission' [patent_app_type] => utility [patent_app_number] => 11/421522 [patent_app_country] => US [patent_app_date] => 2006-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1829 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/427/07427878.pdf [firstpage_image] =>[orig_patent_app_number] => 11421522 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5008619 [patent_doc_number] => 20070279096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-06 [patent_title] => 'USB 2.0 Transmitter Using Only 2.5 Volt CMOS Devices' [patent_app_type] => utility [patent_app_number] => 11/421318 [patent_app_country] => US [patent_app_date] => 2006-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4361 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0279/20070279096.pdf [firstpage_image] =>[orig_patent_app_number] => 11421318 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 152854 [patent_doc_number] => 07683670 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-23 [patent_title] => 'High-speed low-power integrated circuit interconnects' [patent_app_type] => utility [patent_app_number] => 11/421457 [patent_app_country] => US [patent_app_date] => 2006-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 10075 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/683/07683670.pdf [firstpage_image] =>[orig_patent_app_number] => 11421457 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5008617 [patent_doc_number] => 20070279094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-06 [patent_title] => 'LOW-VOLTAGE DIFFERENTIAL SIGNAL DRIVER FOR HIGH-SPEED DIGITAL TRANSMISSION' [patent_app_type] => utility [patent_app_number] => 11/421239 [patent_app_country] => US [patent_app_date] => 2006-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1881 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0279/20070279094.pdf [firstpage_image] =>[orig_patent_app_number] => 11421239 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 253236 [patent_doc_number] => 07579872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-25 [patent_title] => 'Low-voltage differential signal driver for high-speed digital transmission' [patent_app_type] => utility [patent_app_number] => 11/421256 [patent_app_country] => US [patent_app_date] => 2006-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2510 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/579/07579872.pdf [firstpage_image] =>[orig_patent_app_number] => 11421256 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 589092 [patent_doc_number] => 07446568 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-04 [patent_title] => 'Receiver start-up compensation circuit' [patent_app_type] => utility [patent_app_number] => 11/420771 [patent_app_country] => US [patent_app_date] => 2006-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3798 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 320 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/446/07446568.pdf [firstpage_image] =>[orig_patent_app_number] => 11420771 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5208613 [patent_doc_number] => 20070247197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-25 [patent_title] => 'Multi-write memory circuit with a data input and a clock input' [patent_app_type] => utility [patent_app_number] => 11/395017 [patent_app_country] => US [patent_app_date] => 2006-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5837 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0247/20070247197.pdf [firstpage_image] =>[orig_patent_app_number] => 11395017 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5730722 [patent_doc_number] => 20060255836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-16 [patent_title] => 'Clock driver circuit and driving method therefor' [patent_app_type] => utility [patent_app_number] => 11/395506 [patent_app_country] => US [patent_app_date] => 2006-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3355 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0255/20060255836.pdf [firstpage_image] =>[orig_patent_app_number] => 11395506 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 240116 [patent_doc_number] => 07592836 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-09-22 [patent_title] => 'Multi-write memory circuit with multiple data inputs' [patent_app_type] => utility [patent_app_number] => 11/396114 [patent_app_country] => US [patent_app_date] => 2006-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 5869 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/592/07592836.pdf [firstpage_image] =>[orig_patent_app_number] => 11396114 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5751527 [patent_doc_number] => 20060220676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-05 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/393851 [patent_app_country] => US [patent_app_date] => 2006-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7781 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0220/20060220676.pdf [firstpage_image] =>[orig_patent_app_number] => 11393851 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5208601 [patent_doc_number] => 20070247185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-25 [patent_title] => 'Memory system with dynamic termination' [patent_app_type] => utility [patent_app_number] => 11/396277 [patent_app_country] => US [patent_app_date] => 2006-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2407 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0247/20070247185.pdf [firstpage_image] =>[orig_patent_app_number] => 11396277 [rel_patent_id] =>[rel_patent_doc_number] =>)