Search

Steven A. Friday

Examiner (ID: 7266, Phone: (571)270-7932 , Office: P/1756 )

Most Active Art Unit
1756
Art Unit(s)
1724, 1795, 1756
Total Applications
364
Issued Applications
170
Pending Applications
2
Abandoned Applications
193

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 575950 [patent_doc_number] => 07463057 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-12-09 [patent_title] => 'Integrated circuits with adjustable memory element power supplies' [patent_app_type] => utility [patent_app_number] => 11/394033 [patent_app_country] => US [patent_app_date] => 2006-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 27 [patent_no_of_words] => 11746 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/463/07463057.pdf [firstpage_image] =>[orig_patent_app_number] => 11394033 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/394033
Integrated circuits with adjustable memory element power supplies Mar 28, 2006 Issued
Array ( [id] => 221539 [patent_doc_number] => 07609085 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-10-27 [patent_title] => 'Configurable integrated circuit with a 4-to-1 multiplexer' [patent_app_type] => utility [patent_app_number] => 11/371198 [patent_app_country] => US [patent_app_date] => 2006-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 52 [patent_no_of_words] => 16199 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/609/07609085.pdf [firstpage_image] =>[orig_patent_app_number] => 11371198 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/371198
Configurable integrated circuit with a 4-to-1 multiplexer Mar 7, 2006 Issued
Array ( [id] => 338513 [patent_doc_number] => 07504858 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-03-17 [patent_title] => 'Configurable integrated circuit with parallel non-neighboring offset connections' [patent_app_type] => utility [patent_app_number] => 11/371191 [patent_app_country] => US [patent_app_date] => 2006-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 52 [patent_no_of_words] => 16264 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/504/07504858.pdf [firstpage_image] =>[orig_patent_app_number] => 11371191 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/371191
Configurable integrated circuit with parallel non-neighboring offset connections Mar 7, 2006 Issued
Array ( [id] => 323166 [patent_doc_number] => 07518400 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-04-14 [patent_title] => 'Barrel shifter implemented on a configurable integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/371194 [patent_app_country] => US [patent_app_date] => 2006-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 52 [patent_no_of_words] => 16116 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/518/07518400.pdf [firstpage_image] =>[orig_patent_app_number] => 11371194 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/371194
Barrel shifter implemented on a configurable integrated circuit Mar 7, 2006 Issued
11/370546 Soft error upset hardened integrated circuit systems and methods Mar 6, 2006 Abandoned
Array ( [id] => 5681283 [patent_doc_number] => 20060197550 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-07 [patent_title] => 'Adjusting driver stage output impedance' [patent_app_type] => utility [patent_app_number] => 11/364961 [patent_app_country] => US [patent_app_date] => 2006-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6665 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20060197550.pdf [firstpage_image] =>[orig_patent_app_number] => 11364961 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/364961
Adjusting driver stage output impedance Feb 27, 2006 Issued
Array ( [id] => 5186471 [patent_doc_number] => 20070164779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'Feedback circuit for line load compensation and reflection reduction' [patent_app_type] => utility [patent_app_number] => 11/324095 [patent_app_country] => US [patent_app_date] => 2005-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3029 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20070164779.pdf [firstpage_image] =>[orig_patent_app_number] => 11324095 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/324095
Feedback circuit for line load compensation and reflection reduction Dec 29, 2005 Issued
Array ( [id] => 5233899 [patent_doc_number] => 20070126054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-07 [patent_title] => 'Nonvolatile memory devices having insulating spacer and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/315295 [patent_app_country] => US [patent_app_date] => 2005-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2238 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20070126054.pdf [firstpage_image] =>[orig_patent_app_number] => 11315295 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/315295
Nonvolatile memory devices having insulating spacer and manufacturing method thereof Dec 22, 2005 Abandoned
Array ( [id] => 5824204 [patent_doc_number] => 20060061386 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-23 [patent_title] => 'Level conversion circuit for converting voltage amplitude of signal' [patent_app_type] => utility [patent_app_number] => 11/230531 [patent_app_country] => US [patent_app_date] => 2005-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7865 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20060061386.pdf [firstpage_image] =>[orig_patent_app_number] => 11230531 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/230531
Level conversion circuit for converting voltage amplitude of signal Sep 20, 2005 Issued
Array ( [id] => 5104854 [patent_doc_number] => 20070063729 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-22 [patent_title] => 'Negative voltage noise-free circuit for multi-functional pad' [patent_app_type] => utility [patent_app_number] => 11/230387 [patent_app_country] => US [patent_app_date] => 2005-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1792 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20070063729.pdf [firstpage_image] =>[orig_patent_app_number] => 11230387 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/230387
Negative voltage noise-free circuit for multi-functional pad Sep 19, 2005 Issued
Array ( [id] => 315367 [patent_doc_number] => 07525340 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-28 [patent_title] => 'Programmable logic device architecture for accommodating specialized circuitry' [patent_app_type] => utility [patent_app_number] => 11/230002 [patent_app_country] => US [patent_app_date] => 2005-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2883 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/525/07525340.pdf [firstpage_image] =>[orig_patent_app_number] => 11230002 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/230002
Programmable logic device architecture for accommodating specialized circuitry Sep 18, 2005 Issued
Array ( [id] => 7595041 [patent_doc_number] => 07626420 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-12-01 [patent_title] => 'Method, apparatus, and system for synchronously resetting logic circuits' [patent_app_type] => utility [patent_app_number] => 11/229280 [patent_app_country] => US [patent_app_date] => 2005-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3542 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/626/07626420.pdf [firstpage_image] =>[orig_patent_app_number] => 11229280 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/229280
Method, apparatus, and system for synchronously resetting logic circuits Sep 15, 2005 Issued
Array ( [id] => 5104863 [patent_doc_number] => 20070063738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-22 [patent_title] => 'CMOS logic circuitry' [patent_app_type] => utility [patent_app_number] => 11/229287 [patent_app_country] => US [patent_app_date] => 2005-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4063 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20070063738.pdf [firstpage_image] =>[orig_patent_app_number] => 11229287 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/229287
CMOS logic circuitry Sep 15, 2005 Abandoned
Array ( [id] => 5679452 [patent_doc_number] => 20060184808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-17 [patent_title] => 'Distributed supply current switch circuits for enabling individual power domains' [patent_app_type] => utility [patent_app_number] => 11/228912 [patent_app_country] => US [patent_app_date] => 2005-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11323 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20060184808.pdf [firstpage_image] =>[orig_patent_app_number] => 11228912 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/228912
Distributed supply current switch circuits for enabling individual power domains Sep 15, 2005 Issued
Array ( [id] => 104895 [patent_doc_number] => 07729300 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-06-01 [patent_title] => 'Class-B transmitter and replica transmitter for gigabit ethernet applications' [patent_app_type] => utility [patent_app_number] => 11/208227 [patent_app_country] => US [patent_app_date] => 2005-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3219 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/729/07729300.pdf [firstpage_image] =>[orig_patent_app_number] => 11208227 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/208227
Class-B transmitter and replica transmitter for gigabit ethernet applications Aug 18, 2005 Issued
Array ( [id] => 4884434 [patent_doc_number] => 20080258766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-23 [patent_title] => 'Mixed Signal Integrated Circuit' [patent_app_type] => utility [patent_app_number] => 11/573861 [patent_app_country] => US [patent_app_date] => 2005-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4449 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0258/20080258766.pdf [firstpage_image] =>[orig_patent_app_number] => 11573861 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/573861
Mixed signal integrated circuit Aug 10, 2005 Issued
Array ( [id] => 5294284 [patent_doc_number] => 20090009210 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-08 [patent_title] => 'Scan-Testable Logic Circuit' [patent_app_type] => utility [patent_app_number] => 11/572998 [patent_app_country] => US [patent_app_date] => 2005-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6404 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0009/20090009210.pdf [firstpage_image] =>[orig_patent_app_number] => 11572998 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/572998
Scan-Testable Logic Circuit Jul 25, 2005 Abandoned
Array ( [id] => 5163535 [patent_doc_number] => 20070285119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-13 [patent_title] => 'Combinatorial Logic Circuit' [patent_app_type] => utility [patent_app_number] => 11/572915 [patent_app_country] => US [patent_app_date] => 2005-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2380 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0285/20070285119.pdf [firstpage_image] =>[orig_patent_app_number] => 11572915 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/572915
Combinatorial logic circuit Jul 17, 2005 Issued
Array ( [id] => 5073449 [patent_doc_number] => 20070013424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-18 [patent_title] => 'Differential dual-edge triggered multiplexer flip-flop and method' [patent_app_type] => utility [patent_app_number] => 11/184205 [patent_app_country] => US [patent_app_date] => 2005-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4943 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20070013424.pdf [firstpage_image] =>[orig_patent_app_number] => 11184205 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/184205
Differential dual-edge triggered multiplexer flip-flop and method Jul 17, 2005 Abandoned
Array ( [id] => 7590812 [patent_doc_number] => 07663399 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-16 [patent_title] => 'Semiconductor memory device having output drive and delay unit' [patent_app_type] => utility [patent_app_number] => 11/172906 [patent_app_country] => US [patent_app_date] => 2005-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3725 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/663/07663399.pdf [firstpage_image] =>[orig_patent_app_number] => 11172906 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/172906
Semiconductor memory device having output drive and delay unit Jul 4, 2005 Issued
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