
Steven A. Friday
Examiner (ID: 7266, Phone: (571)270-7932 , Office: P/1756 )
| Most Active Art Unit | 1756 |
| Art Unit(s) | 1724, 1795, 1756 |
| Total Applications | 364 |
| Issued Applications | 170 |
| Pending Applications | 2 |
| Abandoned Applications | 193 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 575950
[patent_doc_number] => 07463057
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-12-09
[patent_title] => 'Integrated circuits with adjustable memory element power supplies'
[patent_app_type] => utility
[patent_app_number] => 11/394033
[patent_app_country] => US
[patent_app_date] => 2006-03-29
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/463/07463057.pdf
[firstpage_image] =>[orig_patent_app_number] => 11394033
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/394033 | Integrated circuits with adjustable memory element power supplies | Mar 28, 2006 | Issued |
Array
(
[id] => 221539
[patent_doc_number] => 07609085
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[patent_issue_date] => 2009-10-27
[patent_title] => 'Configurable integrated circuit with a 4-to-1 multiplexer'
[patent_app_type] => utility
[patent_app_number] => 11/371198
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[patent_app_date] => 2006-03-08
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[firstpage_image] =>[orig_patent_app_number] => 11371198
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/371198 | Configurable integrated circuit with a 4-to-1 multiplexer | Mar 7, 2006 | Issued |
Array
(
[id] => 338513
[patent_doc_number] => 07504858
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[patent_issue_date] => 2009-03-17
[patent_title] => 'Configurable integrated circuit with parallel non-neighboring offset connections'
[patent_app_type] => utility
[patent_app_number] => 11/371191
[patent_app_country] => US
[patent_app_date] => 2006-03-08
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/371191 | Configurable integrated circuit with parallel non-neighboring offset connections | Mar 7, 2006 | Issued |
Array
(
[id] => 323166
[patent_doc_number] => 07518400
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2009-04-14
[patent_title] => 'Barrel shifter implemented on a configurable integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 11/371194
[patent_app_country] => US
[patent_app_date] => 2006-03-08
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/518/07518400.pdf
[firstpage_image] =>[orig_patent_app_number] => 11371194
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/371194 | Barrel shifter implemented on a configurable integrated circuit | Mar 7, 2006 | Issued |
| 11/370546 | Soft error upset hardened integrated circuit systems and methods | Mar 6, 2006 | Abandoned |
Array
(
[id] => 5681283
[patent_doc_number] => 20060197550
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[patent_issue_date] => 2006-09-07
[patent_title] => 'Adjusting driver stage output impedance'
[patent_app_type] => utility
[patent_app_number] => 11/364961
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/364961 | Adjusting driver stage output impedance | Feb 27, 2006 | Issued |
Array
(
[id] => 5186471
[patent_doc_number] => 20070164779
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[patent_title] => 'Feedback circuit for line load compensation and reflection reduction'
[patent_app_type] => utility
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[firstpage_image] =>[orig_patent_app_number] => 11324095
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/324095 | Feedback circuit for line load compensation and reflection reduction | Dec 29, 2005 | Issued |
Array
(
[id] => 5233899
[patent_doc_number] => 20070126054
[patent_country] => US
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[patent_issue_date] => 2007-06-07
[patent_title] => 'Nonvolatile memory devices having insulating spacer and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/315295
[patent_app_country] => US
[patent_app_date] => 2005-12-23
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 11315295
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/315295 | Nonvolatile memory devices having insulating spacer and manufacturing method thereof | Dec 22, 2005 | Abandoned |
Array
(
[id] => 5824204
[patent_doc_number] => 20060061386
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-23
[patent_title] => 'Level conversion circuit for converting voltage amplitude of signal'
[patent_app_type] => utility
[patent_app_number] => 11/230531
[patent_app_country] => US
[patent_app_date] => 2005-09-21
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 11230531
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/230531 | Level conversion circuit for converting voltage amplitude of signal | Sep 20, 2005 | Issued |
Array
(
[id] => 5104854
[patent_doc_number] => 20070063729
[patent_country] => US
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[patent_issue_date] => 2007-03-22
[patent_title] => 'Negative voltage noise-free circuit for multi-functional pad'
[patent_app_type] => utility
[patent_app_number] => 11/230387
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[patent_app_date] => 2005-09-20
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[firstpage_image] =>[orig_patent_app_number] => 11230387
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/230387 | Negative voltage noise-free circuit for multi-functional pad | Sep 19, 2005 | Issued |
Array
(
[id] => 315367
[patent_doc_number] => 07525340
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-04-28
[patent_title] => 'Programmable logic device architecture for accommodating specialized circuitry'
[patent_app_type] => utility
[patent_app_number] => 11/230002
[patent_app_country] => US
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[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/525/07525340.pdf
[firstpage_image] =>[orig_patent_app_number] => 11230002
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/230002 | Programmable logic device architecture for accommodating specialized circuitry | Sep 18, 2005 | Issued |
Array
(
[id] => 7595041
[patent_doc_number] => 07626420
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[patent_issue_date] => 2009-12-01
[patent_title] => 'Method, apparatus, and system for synchronously resetting logic circuits'
[patent_app_type] => utility
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[patent_app_date] => 2005-09-16
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[pdf_file] => patents/07/626/07626420.pdf
[firstpage_image] =>[orig_patent_app_number] => 11229280
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/229280 | Method, apparatus, and system for synchronously resetting logic circuits | Sep 15, 2005 | Issued |
Array
(
[id] => 5104863
[patent_doc_number] => 20070063738
[patent_country] => US
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[patent_issue_date] => 2007-03-22
[patent_title] => 'CMOS logic circuitry'
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[firstpage_image] =>[orig_patent_app_number] => 11229287
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/229287 | CMOS logic circuitry | Sep 15, 2005 | Abandoned |
Array
(
[id] => 5679452
[patent_doc_number] => 20060184808
[patent_country] => US
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[patent_issue_date] => 2006-08-17
[patent_title] => 'Distributed supply current switch circuits for enabling individual power domains'
[patent_app_type] => utility
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[firstpage_image] =>[orig_patent_app_number] => 11228912
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/228912 | Distributed supply current switch circuits for enabling individual power domains | Sep 15, 2005 | Issued |
Array
(
[id] => 104895
[patent_doc_number] => 07729300
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[patent_issue_date] => 2010-06-01
[patent_title] => 'Class-B transmitter and replica transmitter for gigabit ethernet applications'
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[patent_app_number] => 11/208227
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[firstpage_image] =>[orig_patent_app_number] => 11208227
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/208227 | Class-B transmitter and replica transmitter for gigabit ethernet applications | Aug 18, 2005 | Issued |
Array
(
[id] => 4884434
[patent_doc_number] => 20080258766
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[patent_issue_date] => 2008-10-23
[patent_title] => 'Mixed Signal Integrated Circuit'
[patent_app_type] => utility
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[firstpage_image] =>[orig_patent_app_number] => 11573861
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/573861 | Mixed signal integrated circuit | Aug 10, 2005 | Issued |
Array
(
[id] => 5294284
[patent_doc_number] => 20090009210
[patent_country] => US
[patent_kind] => A1
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[patent_title] => 'Scan-Testable Logic Circuit'
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[firstpage_image] =>[orig_patent_app_number] => 11572998
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/572998 | Scan-Testable Logic Circuit | Jul 25, 2005 | Abandoned |
Array
(
[id] => 5163535
[patent_doc_number] => 20070285119
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[patent_title] => 'Combinatorial Logic Circuit'
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[firstpage_image] =>[orig_patent_app_number] => 11572915
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/572915 | Combinatorial logic circuit | Jul 17, 2005 | Issued |
Array
(
[id] => 5073449
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/172906 | Semiconductor memory device having output drive and delay unit | Jul 4, 2005 | Issued |