
Steven A. Friday
Examiner (ID: 7266, Phone: (571)270-7932 , Office: P/1756 )
| Most Active Art Unit | 1756 |
| Art Unit(s) | 1724, 1795, 1756 |
| Total Applications | 364 |
| Issued Applications | 170 |
| Pending Applications | 2 |
| Abandoned Applications | 193 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5892907
[patent_doc_number] => 20060001445
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-01-05
[patent_title] => 'Programmable logic block for designing an asynchronous circuit'
[patent_app_type] => utility
[patent_app_number] => 11/171217
[patent_app_country] => US
[patent_app_date] => 2005-07-01
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[pdf_file] => publications/A1/0001/20060001445.pdf
[firstpage_image] =>[orig_patent_app_number] => 11171217
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/171217 | Programmable logic block for designing an asynchronous circuit | Jun 30, 2005 | Issued |
Array
(
[id] => 170038
[patent_doc_number] => 07667546
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-02-23
[patent_title] => 'LVDS receiver for controlling current based on frequency and method of operating the LVDS receiver'
[patent_app_type] => utility
[patent_app_number] => 11/173485
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/173485 | LVDS receiver for controlling current based on frequency and method of operating the LVDS receiver | Jun 29, 2005 | Issued |
Array
(
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[patent_issue_date] => 2007-01-11
[patent_title] => 'High-speed differential receiver'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/171723 | High-speed differential receiver | Jun 29, 2005 | Issued |
Array
(
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[patent_kind] => B2
[patent_issue_date] => 2010-02-16
[patent_title] => 'Scannable dynamic circuit latch'
[patent_app_type] => utility
[patent_app_number] => 11/171695
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 11171695
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/171695 | Scannable dynamic circuit latch | Jun 29, 2005 | Issued |
Array
(
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[patent_title] => 'Distributed power and clock management in a computerized system'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/170770 | Distributed power and clock management in a computerized system | Jun 28, 2005 | Abandoned |
Array
(
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[patent_kind] => A1
[patent_issue_date] => 2007-01-11
[patent_title] => 'I/O circuitry for reducing ground bounce and VCC sag in integrated circuit devices'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/172568 | I/O circuitry for reducing ground bounce and VCC sag in integrated circuit devices | Jun 28, 2005 | Issued |
Array
(
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[patent_doc_number] => 07538577
[patent_country] => US
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[patent_issue_date] => 2009-05-26
[patent_title] => 'System and method for configuring a field programmable gate array'
[patent_app_type] => utility
[patent_app_number] => 11/172092
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[firstpage_image] =>[orig_patent_app_number] => 11172092
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/172092 | System and method for configuring a field programmable gate array | Jun 28, 2005 | Issued |
Array
(
[id] => 5818397
[patent_doc_number] => 20060022710
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[patent_title] => 'Integrated circuit having an input/output terminal configurable within a given voltage range'
[patent_app_type] => utility
[patent_app_number] => 11/170760
[patent_app_country] => US
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[patent_drawing_sheets_cnt] => 2
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/170760 | Integrated circuit having an input/output terminal configurable within a given voltage range | Jun 27, 2005 | Abandoned |
Array
(
[id] => 83166
[patent_doc_number] => 07746096
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[patent_kind] => B1
[patent_issue_date] => 2010-06-29
[patent_title] => 'Impedance buffer and method'
[patent_app_type] => utility
[patent_app_number] => 11/138823
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[firstpage_image] =>[orig_patent_app_number] => 11138823
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/138823 | Impedance buffer and method | May 25, 2005 | Issued |
Array
(
[id] => 800694
[patent_doc_number] => 07425842
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-09-16
[patent_title] => 'Logic basic cell'
[patent_app_type] => utility
[patent_app_number] => 11/131452
[patent_app_country] => US
[patent_app_date] => 2005-05-16
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[pdf_file] => patents/07/425/07425842.pdf
[firstpage_image] =>[orig_patent_app_number] => 11131452
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/131452 | Logic basic cell | May 15, 2005 | Issued |
Array
(
[id] => 5699103
[patent_doc_number] => 20060215787
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-09-28
[patent_title] => 'Data receiver including a transconductance amplifier'
[patent_app_type] => utility
[patent_app_number] => 11/091227
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[firstpage_image] =>[orig_patent_app_number] => 11091227
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/091227 | Data receiver including a transconductance amplifier | Mar 27, 2005 | Issued |
Array
(
[id] => 260560
[patent_doc_number] => 07573290
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[patent_title] => 'Data output driver for reducing noise'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/056475 | Data output driver for reducing noise | Feb 10, 2005 | Issued |
Array
(
[id] => 4533825
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[patent_title] => 'Logic system for DPA resistance and/or side channel attack resistance'
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Array
(
[id] => 7599343
[patent_doc_number] => 07583105
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[patent_kind] => B2
[patent_issue_date] => 2009-09-01
[patent_title] => 'Pull-up circuit'
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[patent_app_number] => 10/597089
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[firstpage_image] =>[orig_patent_app_number] => 10597089
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/597089 | Pull-up circuit | Dec 28, 2004 | Issued |
Array
(
[id] => 5651123
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[patent_title] => 'Utilizing fuses to store control parameters for external system components'
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[firstpage_image] =>[orig_patent_app_number] => 11016214
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/016214 | Utilizing fuses to store control parameters for external system components | Dec 16, 2004 | Abandoned |
Array
(
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Array
(
[id] => 264308
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Array
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Array
(
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[patent_title] => 'Interface circuit power reduction'
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Array
(
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[patent_title] => 'Level shifting circuit between isolated systems'
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[firstpage_image] =>[orig_patent_app_number] => 10535557
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/535557 | Level shifting circuit between isolated systems | Nov 14, 2003 | Abandoned |