Search

Steven A. Friday

Examiner (ID: 7266, Phone: (571)270-7932 , Office: P/1756 )

Most Active Art Unit
1756
Art Unit(s)
1724, 1795, 1756
Total Applications
364
Issued Applications
170
Pending Applications
2
Abandoned Applications
193

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5892907 [patent_doc_number] => 20060001445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-05 [patent_title] => 'Programmable logic block for designing an asynchronous circuit' [patent_app_type] => utility [patent_app_number] => 11/171217 [patent_app_country] => US [patent_app_date] => 2005-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5955 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20060001445.pdf [firstpage_image] =>[orig_patent_app_number] => 11171217 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/171217
Programmable logic block for designing an asynchronous circuit Jun 30, 2005 Issued
Array ( [id] => 170038 [patent_doc_number] => 07667546 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-23 [patent_title] => 'LVDS receiver for controlling current based on frequency and method of operating the LVDS receiver' [patent_app_type] => utility [patent_app_number] => 11/173485 [patent_app_country] => US [patent_app_date] => 2005-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4240 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/667/07667546.pdf [firstpage_image] =>[orig_patent_app_number] => 11173485 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/173485
LVDS receiver for controlling current based on frequency and method of operating the LVDS receiver Jun 29, 2005 Issued
Array ( [id] => 4992658 [patent_doc_number] => 20070008002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-11 [patent_title] => 'High-speed differential receiver' [patent_app_type] => utility [patent_app_number] => 11/171723 [patent_app_country] => US [patent_app_date] => 2005-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2542 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20070008002.pdf [firstpage_image] =>[orig_patent_app_number] => 11171723 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/171723
High-speed differential receiver Jun 29, 2005 Issued
Array ( [id] => 7590805 [patent_doc_number] => 07663408 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-16 [patent_title] => 'Scannable dynamic circuit latch' [patent_app_type] => utility [patent_app_number] => 11/171695 [patent_app_country] => US [patent_app_date] => 2005-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2778 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/663/07663408.pdf [firstpage_image] =>[orig_patent_app_number] => 11171695 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/171695
Scannable dynamic circuit latch Jun 29, 2005 Issued
Array ( [id] => 4992667 [patent_doc_number] => 20070008011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-11 [patent_title] => 'Distributed power and clock management in a computerized system' [patent_app_type] => utility [patent_app_number] => 11/170770 [patent_app_country] => US [patent_app_date] => 2005-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3605 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20070008011.pdf [firstpage_image] =>[orig_patent_app_number] => 11170770 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/170770
Distributed power and clock management in a computerized system Jun 28, 2005 Abandoned
Array ( [id] => 4992647 [patent_doc_number] => 20070007991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-11 [patent_title] => 'I/O circuitry for reducing ground bounce and VCC sag in integrated circuit devices' [patent_app_type] => utility [patent_app_number] => 11/172568 [patent_app_country] => US [patent_app_date] => 2005-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3882 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20070007991.pdf [firstpage_image] =>[orig_patent_app_number] => 11172568 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/172568
I/O circuitry for reducing ground bounce and VCC sag in integrated circuit devices Jun 28, 2005 Issued
Array ( [id] => 300373 [patent_doc_number] => 07538577 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-26 [patent_title] => 'System and method for configuring a field programmable gate array' [patent_app_type] => utility [patent_app_number] => 11/172092 [patent_app_country] => US [patent_app_date] => 2005-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6585 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/538/07538577.pdf [firstpage_image] =>[orig_patent_app_number] => 11172092 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/172092
System and method for configuring a field programmable gate array Jun 28, 2005 Issued
Array ( [id] => 5818397 [patent_doc_number] => 20060022710 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-02 [patent_title] => 'Integrated circuit having an input/output terminal configurable within a given voltage range' [patent_app_type] => utility [patent_app_number] => 11/170760 [patent_app_country] => US [patent_app_date] => 2005-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2800 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20060022710.pdf [firstpage_image] =>[orig_patent_app_number] => 11170760 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/170760
Integrated circuit having an input/output terminal configurable within a given voltage range Jun 27, 2005 Abandoned
Array ( [id] => 83166 [patent_doc_number] => 07746096 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-06-29 [patent_title] => 'Impedance buffer and method' [patent_app_type] => utility [patent_app_number] => 11/138823 [patent_app_country] => US [patent_app_date] => 2005-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3062 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/746/07746096.pdf [firstpage_image] =>[orig_patent_app_number] => 11138823 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/138823
Impedance buffer and method May 25, 2005 Issued
Array ( [id] => 800694 [patent_doc_number] => 07425842 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-16 [patent_title] => 'Logic basic cell' [patent_app_type] => utility [patent_app_number] => 11/131452 [patent_app_country] => US [patent_app_date] => 2005-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 9172 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 318 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/425/07425842.pdf [firstpage_image] =>[orig_patent_app_number] => 11131452 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/131452
Logic basic cell May 15, 2005 Issued
Array ( [id] => 5699103 [patent_doc_number] => 20060215787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-28 [patent_title] => 'Data receiver including a transconductance amplifier' [patent_app_type] => utility [patent_app_number] => 11/091227 [patent_app_country] => US [patent_app_date] => 2005-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2024 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0215/20060215787.pdf [firstpage_image] =>[orig_patent_app_number] => 11091227 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/091227
Data receiver including a transconductance amplifier Mar 27, 2005 Issued
Array ( [id] => 260560 [patent_doc_number] => 07573290 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-11 [patent_title] => 'Data output driver for reducing noise' [patent_app_type] => utility [patent_app_number] => 11/056475 [patent_app_country] => US [patent_app_date] => 2005-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4485 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/573/07573290.pdf [firstpage_image] =>[orig_patent_app_number] => 11056475 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/056475
Data output driver for reducing noise Feb 10, 2005 Issued
Array ( [id] => 4533825 [patent_doc_number] => 07924057 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-12 [patent_title] => 'Logic system for DPA resistance and/or side channel attack resistance' [patent_app_type] => utility [patent_app_number] => 10/586846 [patent_app_country] => US [patent_app_date] => 2005-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 8338 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/924/07924057.pdf [firstpage_image] =>[orig_patent_app_number] => 10586846 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/586846
Logic system for DPA resistance and/or side channel attack resistance Feb 10, 2005 Issued
Array ( [id] => 7599343 [patent_doc_number] => 07583105 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-01 [patent_title] => 'Pull-up circuit' [patent_app_type] => utility [patent_app_number] => 10/597089 [patent_app_country] => US [patent_app_date] => 2004-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3239 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/583/07583105.pdf [firstpage_image] =>[orig_patent_app_number] => 10597089 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/597089
Pull-up circuit Dec 28, 2004 Issued
Array ( [id] => 5651123 [patent_doc_number] => 20060136858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-22 [patent_title] => 'Utilizing fuses to store control parameters for external system components' [patent_app_type] => utility [patent_app_number] => 11/016214 [patent_app_country] => US [patent_app_date] => 2004-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8672 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20060136858.pdf [firstpage_image] =>[orig_patent_app_number] => 11016214 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/016214
Utilizing fuses to store control parameters for external system components Dec 16, 2004 Abandoned
Array ( [id] => 5863565 [patent_doc_number] => 20060097695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-11 [patent_title] => 'Analog OR circuit with wide input voltage detection range' [patent_app_type] => utility [patent_app_number] => 10/985866 [patent_app_country] => US [patent_app_date] => 2004-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4228 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20060097695.pdf [firstpage_image] =>[orig_patent_app_number] => 10985866 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/985866
Analog OR circuit with wide input voltage detection range Nov 9, 2004 Abandoned
Array ( [id] => 264308 [patent_doc_number] => 07570076 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-04 [patent_title] => 'Segmented programmable capacitor array for improved density and reduced leakage' [patent_app_type] => utility [patent_app_number] => 10/964802 [patent_app_country] => US [patent_app_date] => 2004-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4620 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/570/07570076.pdf [firstpage_image] =>[orig_patent_app_number] => 10964802 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/964802
Segmented programmable capacitor array for improved density and reduced leakage Oct 12, 2004 Issued
Array ( [id] => 373814 [patent_doc_number] => 07474119 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-06 [patent_title] => 'Logic circuit apparatus and timeshare operating method of a programmable logic circuit' [patent_app_type] => utility [patent_app_number] => 10/948702 [patent_app_country] => US [patent_app_date] => 2004-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9801 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/474/07474119.pdf [firstpage_image] =>[orig_patent_app_number] => 10948702 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/948702
Logic circuit apparatus and timeshare operating method of a programmable logic circuit Sep 23, 2004 Issued
Array ( [id] => 7243111 [patent_doc_number] => 20050073198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-07 [patent_title] => 'Interface circuit power reduction' [patent_app_type] => utility [patent_app_number] => 10/944091 [patent_app_country] => US [patent_app_date] => 2004-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7170 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20050073198.pdf [firstpage_image] =>[orig_patent_app_number] => 10944091 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/944091
Interface circuit power reduction Sep 16, 2004 Issued
Array ( [id] => 5892909 [patent_doc_number] => 20060001447 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-05 [patent_title] => 'Level shifting circuit between isolated systems' [patent_app_type] => utility [patent_app_number] => 10/535557 [patent_app_country] => US [patent_app_date] => 2003-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5715 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20060001447.pdf [firstpage_image] =>[orig_patent_app_number] => 10535557 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/535557
Level shifting circuit between isolated systems Nov 14, 2003 Abandoned
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