Search

Steven A. Macdonald

Examiner (ID: 4855, Phone: (571)272-8763 , Office: P/3676 )

Most Active Art Unit
3674
Art Unit(s)
3676, 3674
Total Applications
793
Issued Applications
606
Pending Applications
62
Abandoned Applications
144

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 415171 [patent_doc_number] => 07279351 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-09 [patent_title] => 'Method of passivating semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/416100 [patent_app_country] => US [patent_app_date] => 2006-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1728 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/279/07279351.pdf [firstpage_image] =>[orig_patent_app_number] => 11416100 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/416100
Method of passivating semiconductor device May 2, 2006 Issued
Array ( [id] => 5903395 [patent_doc_number] => 20060046345 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'Method for fabricating a silicon carbide interconnect for semiconductor components using heating and oxidizing' [patent_app_type] => utility [patent_app_number] => 11/259508 [patent_app_country] => US [patent_app_date] => 2005-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9993 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20060046345.pdf [firstpage_image] =>[orig_patent_app_number] => 11259508 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/259508
Method for fabricating a silicon carbide interconnect for semiconductor components using heating Oct 25, 2005 Issued
Array ( [id] => 630359 [patent_doc_number] => 07132319 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-07 [patent_title] => 'Transparent double-injection field-effect transistor' [patent_app_type] => utility [patent_app_number] => 11/237444 [patent_app_country] => US [patent_app_date] => 2005-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4131 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/132/07132319.pdf [firstpage_image] =>[orig_patent_app_number] => 11237444 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/237444
Transparent double-injection field-effect transistor Sep 26, 2005 Issued
Array ( [id] => 5905407 [patent_doc_number] => 20060047355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'Method and apparatus for adjusting characteristics of multi-layer electronic components' [patent_app_type] => utility [patent_app_number] => 11/211695 [patent_app_country] => US [patent_app_date] => 2005-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5953 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20060047355.pdf [firstpage_image] =>[orig_patent_app_number] => 11211695 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/211695
Method and apparatus for adjusting characteristics of multi-layer electronic components Aug 25, 2005 Abandoned
Array ( [id] => 7111237 [patent_doc_number] => 20050208693 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-22 [patent_title] => 'Method of fabricating an in-plane switching liquid crystal display device' [patent_app_type] => utility [patent_app_number] => 11/126266 [patent_app_country] => US [patent_app_date] => 2005-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6730 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0208/20050208693.pdf [firstpage_image] =>[orig_patent_app_number] => 11126266 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/126266
Method of fabricating an in-plane switching liquid crystal display device May 10, 2005 Issued
10/520865 Method of forming an electrostatic discharge protecting device and integrated circuit arrangment comprising such a device Jan 6, 2005 Abandoned
Array ( [id] => 5649148 [patent_doc_number] => 20060134883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-22 [patent_title] => 'Systems and methods for electrical contacts to arrays of vertically aligned nanorods' [patent_app_type] => utility [patent_app_number] => 11/015665 [patent_app_country] => US [patent_app_date] => 2004-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4918 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20060134883.pdf [firstpage_image] =>[orig_patent_app_number] => 11015665 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/015665
Systems and methods for electrical contacts to arrays of vertically aligned nanorods Dec 19, 2004 Issued
Array ( [id] => 7127503 [patent_doc_number] => 20050059247 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-17 [patent_title] => 'Method for manufacturing SiC substrate' [patent_app_type] => utility [patent_app_number] => 10/942706 [patent_app_country] => US [patent_app_date] => 2004-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6459 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20050059247.pdf [firstpage_image] =>[orig_patent_app_number] => 10942706 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/942706
Method for manufacturing SiC substrate Sep 14, 2004 Abandoned
Array ( [id] => 7235441 [patent_doc_number] => 20050139831 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/939973 [patent_app_country] => US [patent_app_date] => 2004-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5923 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20050139831.pdf [firstpage_image] =>[orig_patent_app_number] => 10939973 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/939973
Semiconductor integrated circuit Sep 13, 2004 Issued
Array ( [id] => 7080588 [patent_doc_number] => 20050045968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-03 [patent_title] => 'Semiconductor device with borderless contact structure and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 10/939266 [patent_app_country] => US [patent_app_date] => 2004-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 5871 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20050045968.pdf [firstpage_image] =>[orig_patent_app_number] => 10939266 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/939266
Semiconductor device with borderless contact structure and method of manufacturing the same Sep 9, 2004 Abandoned
Array ( [id] => 5903606 [patent_doc_number] => 20060046472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'Barrier layer, IC via, and IC line forming methods' [patent_app_type] => utility [patent_app_number] => 10/932156 [patent_app_country] => US [patent_app_date] => 2004-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4533 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20060046472.pdf [firstpage_image] =>[orig_patent_app_number] => 10932156 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/932156
Barrier layer, IC via, and IC line forming methods Aug 31, 2004 Issued
Array ( [id] => 419104 [patent_doc_number] => 07276779 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-02 [patent_title] => 'III-V group nitride system semiconductor substrate' [patent_app_type] => utility [patent_app_number] => 10/928482 [patent_app_country] => US [patent_app_date] => 2004-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 8833 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/276/07276779.pdf [firstpage_image] =>[orig_patent_app_number] => 10928482 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/928482
III-V group nitride system semiconductor substrate Aug 29, 2004 Issued
Array ( [id] => 7033274 [patent_doc_number] => 20050031783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-10 [patent_title] => 'System for and method of manufacturing a large-area backplane by use of a small-area shadow mask' [patent_app_type] => utility [patent_app_number] => 10/925726 [patent_app_country] => US [patent_app_date] => 2004-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4831 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20050031783.pdf [firstpage_image] =>[orig_patent_app_number] => 10925726 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/925726
System for and method of manufacturing a large-area backplane by use of a small-area shadow mask Aug 24, 2004 Issued
Array ( [id] => 5591007 [patent_doc_number] => 20060040459 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-23 [patent_title] => 'Method to produce thin film resistor with no resistor head using dry etch' [patent_app_type] => utility [patent_app_number] => 10/922296 [patent_app_country] => US [patent_app_date] => 2004-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1692 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20060040459.pdf [firstpage_image] =>[orig_patent_app_number] => 10922296 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/922296
Method to produce thin film resistor with no resistor head using dry etch Aug 18, 2004 Abandoned
Array ( [id] => 452994 [patent_doc_number] => 07247546 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-24 [patent_title] => 'Method of forming strained silicon materials with improved thermal conductivity' [patent_app_type] => utility [patent_app_number] => 10/710826 [patent_app_country] => US [patent_app_date] => 2004-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2059 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/247/07247546.pdf [firstpage_image] =>[orig_patent_app_number] => 10710826 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/710826
Method of forming strained silicon materials with improved thermal conductivity Aug 4, 2004 Issued
Array ( [id] => 435865 [patent_doc_number] => 07262121 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-28 [patent_title] => 'Integrated circuit and methods of redistributing bondpad locations' [patent_app_type] => utility [patent_app_number] => 10/903796 [patent_app_country] => US [patent_app_date] => 2004-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 4364 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/262/07262121.pdf [firstpage_image] =>[orig_patent_app_number] => 10903796 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/903796
Integrated circuit and methods of redistributing bondpad locations Jul 28, 2004 Issued
Array ( [id] => 397471 [patent_doc_number] => 07294440 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-13 [patent_title] => 'Method to selectively correct critical dimension errors in the semiconductor industry' [patent_app_type] => utility [patent_app_number] => 10/710602 [patent_app_country] => US [patent_app_date] => 2004-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4173 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/294/07294440.pdf [firstpage_image] =>[orig_patent_app_number] => 10710602 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/710602
Method to selectively correct critical dimension errors in the semiconductor industry Jul 22, 2004 Issued
Array ( [id] => 7089187 [patent_doc_number] => 20050009300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-13 [patent_title] => 'Electronic semiconductor device having a thermal spreader' [patent_app_type] => utility [patent_app_number] => 10/893021 [patent_app_country] => US [patent_app_date] => 2004-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2013 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0009/20050009300.pdf [firstpage_image] =>[orig_patent_app_number] => 10893021 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/893021
Electronic semiconductor device having a thermal spreader Jul 15, 2004 Issued
Array ( [id] => 5895022 [patent_doc_number] => 20060003561 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-05 [patent_title] => 'Method of making a semiconductor device having a strained semiconductor layer' [patent_app_type] => utility [patent_app_number] => 10/880685 [patent_app_country] => US [patent_app_date] => 2004-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1896 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20060003561.pdf [firstpage_image] =>[orig_patent_app_number] => 10880685 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/880685
Method of making a semiconductor device having a strained semiconductor layer Jun 29, 2004 Issued
Array ( [id] => 5895053 [patent_doc_number] => 20060003592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-05 [patent_title] => 'System and method for processing a substrate using supercritical carbon dioxide processing' [patent_app_type] => utility [patent_app_number] => 10/881456 [patent_app_country] => US [patent_app_date] => 2004-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6260 [patent_no_of_claims] => 65 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20060003592.pdf [firstpage_image] =>[orig_patent_app_number] => 10881456 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/881456
System and method for processing a substrate using supercritical carbon dioxide processing Jun 29, 2004 Issued
Menu