
Steven C. Bishop
Examiner (ID: 11061)
| Most Active Art Unit | 3202 |
| Art Unit(s) | 3202, 3722, 3209, 2899 |
| Total Applications | 1994 |
| Issued Applications | 1760 |
| Pending Applications | 96 |
| Abandoned Applications | 138 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8213882
[patent_doc_number] => 20120131307
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-05-24
[patent_title] => 'DATA STRUCTURE FOR ENFORCING CONSISTENT PER-PHYSICAL PAGE CACHEABILITY ATTRIBUTES'
[patent_app_type] => utility
[patent_app_number] => 13/363050
[patent_app_country] => US
[patent_app_date] => 2012-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 4799
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0131/20120131307.pdf
[firstpage_image] =>[orig_patent_app_number] => 13363050
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/363050 | Data structure for enforcing consistent per-physical page cacheability attributes | Jan 30, 2012 | Issued |
Array
(
[id] => 8213821
[patent_doc_number] => 20120131269
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-05-24
[patent_title] => 'ADAPTIVE MEMORY SYSTEM FOR ENHANCING THE PERFORMANCE OF AN EXTERNAL COMPUTING DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/363151
[patent_app_country] => US
[patent_app_date] => 2012-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 7124
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0131/20120131269.pdf
[firstpage_image] =>[orig_patent_app_number] => 13363151
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/363151 | Adaptive memory system for enhancing the performance of an external computing device | Jan 30, 2012 | Issued |
Array
(
[id] => 8952957
[patent_doc_number] => 20130198738
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-08-01
[patent_title] => 'INPUT/OUTPUT OPERATIONS AT A VIRTUAL BLOCK DEVICE OF A STORAGE SERVER'
[patent_app_type] => utility
[patent_app_number] => 13/360956
[patent_app_country] => US
[patent_app_date] => 2012-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 11193
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13360956
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/360956 | Input/output operations at a virtual block device of a storage server | Jan 29, 2012 | Issued |
Array
(
[id] => 8177075
[patent_doc_number] => 20120110592
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-05-03
[patent_title] => 'Autonomic Self-Tuning Of Database Management System In Dynamic Logical Partitioning Environment'
[patent_app_type] => utility
[patent_app_number] => 13/333552
[patent_app_country] => US
[patent_app_date] => 2011-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5145
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0110/20120110592.pdf
[firstpage_image] =>[orig_patent_app_number] => 13333552
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/333552 | Autonomic self-tuning of database management system in dynamic logical partitioning environment | Dec 20, 2011 | Issued |
Array
(
[id] => 8097813
[patent_doc_number] => 20120084512
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-04-05
[patent_title] => 'FAST UNALIGNED CACHE ACCESS SYSTEM AND METHOD'
[patent_app_type] => utility
[patent_app_number] => 13/324917
[patent_app_country] => US
[patent_app_date] => 2011-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4509
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0084/20120084512.pdf
[firstpage_image] =>[orig_patent_app_number] => 13324917
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/324917 | Fast unaligned cache access system and method | Dec 12, 2011 | Issued |
Array
(
[id] => 8703784
[patent_doc_number] => 08397019
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-03-12
[patent_title] => 'Memory for accessing multiple sectors of information substantially concurrently'
[patent_app_type] => utility
[patent_app_number] => 13/323144
[patent_app_country] => US
[patent_app_date] => 2011-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 21
[patent_no_of_words] => 13162
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 241
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13323144
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/323144 | Memory for accessing multiple sectors of information substantially concurrently | Dec 11, 2011 | Issued |
Array
(
[id] => 8058893
[patent_doc_number] => 20120079177
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-03-29
[patent_title] => 'MEMORY INTERLEAVE FOR HETEROGENEOUS COMPUTING'
[patent_app_type] => utility
[patent_app_number] => 13/311378
[patent_app_country] => US
[patent_app_date] => 2011-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 15819
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0079/20120079177.pdf
[firstpage_image] =>[orig_patent_app_number] => 13311378
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/311378 | Memory interleave for heterogeneous computing | Dec 4, 2011 | Issued |
Array
(
[id] => 8349145
[patent_doc_number] => 20120210068
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-08-16
[patent_title] => 'SYSTEMS AND METHODS FOR A MULTI-LEVEL CACHE'
[patent_app_type] => utility
[patent_app_number] => 13/288005
[patent_app_country] => US
[patent_app_date] => 2011-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 34
[patent_figures_cnt] => 34
[patent_no_of_words] => 32033
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13288005
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/288005 | Systems and methods for a multi-level cache | Nov 1, 2011 | Issued |
Array
(
[id] => 9954293
[patent_doc_number] => 09003104
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-04-07
[patent_title] => 'Systems and methods for a file-level cache'
[patent_app_type] => utility
[patent_app_number] => 13/287998
[patent_app_country] => US
[patent_app_date] => 2011-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 33
[patent_figures_cnt] => 37
[patent_no_of_words] => 32047
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13287998
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/287998 | Systems and methods for a file-level cache | Nov 1, 2011 | Issued |
Array
(
[id] => 9578761
[patent_doc_number] => 08769196
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-07-01
[patent_title] => 'Configuring I/O cache'
[patent_app_type] => utility
[patent_app_number] => 13/250315
[patent_app_country] => US
[patent_app_date] => 2011-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 7058
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13250315
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/250315 | Configuring I/O cache | Sep 29, 2011 | Issued |
Array
(
[id] => 9926235
[patent_doc_number] => 08984220
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-03-17
[patent_title] => 'Storage path management host view'
[patent_app_type] => utility
[patent_app_number] => 13/250314
[patent_app_country] => US
[patent_app_date] => 2011-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 36
[patent_no_of_words] => 11345
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 225
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13250314
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/250314 | Storage path management host view | Sep 29, 2011 | Issued |
Array
(
[id] => 8176606
[patent_doc_number] => 20120110306
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-05-03
[patent_title] => 'TRANSLATED MEMORY PROTECTION APPARATUS FOR AN ADVANCED MICROPROCESSOR'
[patent_app_type] => utility
[patent_app_number] => 13/243943
[patent_app_country] => US
[patent_app_date] => 2011-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 20787
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0110/20120110306.pdf
[firstpage_image] =>[orig_patent_app_number] => 13243943
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/243943 | Translated memory protection apparatus for an advanced microprocessor | Sep 22, 2011 | Issued |
Array
(
[id] => 7721985
[patent_doc_number] => 20120011320
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-01-12
[patent_title] => 'COMPUTER SYSTEM AND MANAGEMENT METHOD FOR THE TRANSFER AND REPLICATION OF DATA AMONG SEVERAL STORAGE DEVICES'
[patent_app_type] => utility
[patent_app_number] => 13/239982
[patent_app_country] => US
[patent_app_date] => 2011-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 17010
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0011/20120011320.pdf
[firstpage_image] =>[orig_patent_app_number] => 13239982
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/239982 | Computer system and management method for the transfer and replication of data among several storage devices | Sep 21, 2011 | Issued |
Array
(
[id] => 8407805
[patent_doc_number] => 20120239873
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-09-20
[patent_title] => 'Memory access system and method for optimizing SDRAM bandwidth'
[patent_app_type] => utility
[patent_app_number] => 13/137643
[patent_app_country] => US
[patent_app_date] => 2011-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5144
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13137643
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/137643 | Memory access system and method for optimizing SDRAM bandwidth | Aug 30, 2011 | Abandoned |
Array
(
[id] => 9555577
[patent_doc_number] => 08762648
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-06-24
[patent_title] => 'Storage system, control apparatus and control method therefor'
[patent_app_type] => utility
[patent_app_number] => 13/137446
[patent_app_country] => US
[patent_app_date] => 2011-08-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 30
[patent_no_of_words] => 26299
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 196
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13137446
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/137446 | Storage system, control apparatus and control method therefor | Aug 15, 2011 | Issued |
Array
(
[id] => 8661249
[patent_doc_number] => 20130042078
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-02-14
[patent_title] => 'Snoop filter and non-inclusive shared cache memory'
[patent_app_type] => utility
[patent_app_number] => 13/137359
[patent_app_country] => US
[patent_app_date] => 2011-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4986
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13137359
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/137359 | Snoop filter and non-inclusive shared cache memory | Aug 7, 2011 | Issued |
Array
(
[id] => 7575400
[patent_doc_number] => 20110271056
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-11-03
[patent_title] => 'MULTITHREADED CLUSTERED MICROARCHITECTURE WITH DYNAMIC BACK-END ASSIGNMENT'
[patent_app_type] => utility
[patent_app_number] => 13/184424
[patent_app_country] => US
[patent_app_date] => 2011-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5797
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0271/20110271056.pdf
[firstpage_image] =>[orig_patent_app_number] => 13184424
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/184424 | Multithreaded clustered microarchitecture with dynamic back-end assignment | Jul 14, 2011 | Issued |
Array
(
[id] => 9752201
[patent_doc_number] => 08843690
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-09-23
[patent_title] => 'Memory conflicts learning capability'
[patent_app_type] => utility
[patent_app_number] => 13/179709
[patent_app_country] => US
[patent_app_date] => 2011-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4187
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13179709
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/179709 | Memory conflicts learning capability | Jul 10, 2011 | Issued |
Array
(
[id] => 9404675
[patent_doc_number] => 08694739
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-04-08
[patent_title] => 'Multiple disparate wireless units sharing of antennas'
[patent_app_type] => utility
[patent_app_number] => 13/176734
[patent_app_country] => US
[patent_app_date] => 2011-07-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3838
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13176734
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/176734 | Multiple disparate wireless units sharing of antennas | Jul 4, 2011 | Issued |
Array
(
[id] => 6020185
[patent_doc_number] => 20110225356
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-09-15
[patent_title] => 'Method for Determining Allocation of Tape Drive Resources for a Secure Data Erase Process'
[patent_app_type] => utility
[patent_app_number] => 13/115054
[patent_app_country] => US
[patent_app_date] => 2011-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 8540
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0225/20110225356.pdf
[firstpage_image] =>[orig_patent_app_number] => 13115054
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/115054 | Method for determining allocation of tape drive resources for a secure data erase process | May 23, 2011 | Issued |