Search

Steven G. Snyder

Examiner (ID: 7148, Phone: (571)270-1971 , Office: P/2184 )

Most Active Art Unit
2184
Art Unit(s)
2184
Total Applications
1026
Issued Applications
801
Pending Applications
59
Abandoned Applications
180

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20513362 [patent_doc_number] => 20260037463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-05 [patent_title] => SYSTEMS AND METHODS FOR PERFORMING DIRECT MEMORY ACCESS DATA TRANSFERS [patent_app_type] => utility [patent_app_number] => 18/789998 [patent_app_country] => US [patent_app_date] => 2024-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 50705 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18789998 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/789998
SYSTEMS AND METHODS FOR PERFORMING DIRECT MEMORY ACCESS DATA TRANSFERS Jul 30, 2024 Pending
Array ( [id] => 20623921 [patent_doc_number] => 12591429 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-31 [patent_title] => Memory interface [patent_app_type] => utility [patent_app_number] => 18/789121 [patent_app_country] => US [patent_app_date] => 2024-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2599 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 419 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18789121 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/789121
Memory interface Jul 29, 2024 Issued
Array ( [id] => 19573878 [patent_doc_number] => 20240378170 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => RETIMER PATH CONTROL METHOD, APPARATUS, AND SYSTEM [patent_app_type] => utility [patent_app_number] => 18/783056 [patent_app_country] => US [patent_app_date] => 2024-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29499 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18783056 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/783056
Retimer path control method, apparatus, and system Jul 23, 2024 Issued
Array ( [id] => 20487499 [patent_doc_number] => 20260023698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-22 [patent_title] => Bandwidth Management of a Serial Interface [patent_app_type] => utility [patent_app_number] => 18/780155 [patent_app_country] => US [patent_app_date] => 2024-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11285 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18780155 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/780155
Bandwidth Management of a Serial Interface Jul 21, 2024 Pending
Array ( [id] => 20530964 [patent_doc_number] => 12549409 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Semiconductor device and communication system for updating setting data of multiple channels [patent_app_type] => utility [patent_app_number] => 18/753679 [patent_app_country] => US [patent_app_date] => 2024-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 1060 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18753679 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/753679
Semiconductor device and communication system for updating setting data of multiple channels Jun 24, 2024 Issued
Array ( [id] => 20550471 [patent_doc_number] => 12561264 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-24 [patent_title] => Scalable data structure for aggregating BMC input and output over serdes for data center and server nodes system and method [patent_app_type] => utility [patent_app_number] => 18/744582 [patent_app_country] => US [patent_app_date] => 2024-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 1750 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18744582 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/744582
Scalable data structure for aggregating BMC input and output over serdes for data center and server nodes system and method Jun 13, 2024 Issued
Array ( [id] => 19979339 [patent_doc_number] => 12346816 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-01 [patent_title] => Neural networks for embedded devices [patent_app_type] => utility [patent_app_number] => 18/664035 [patent_app_country] => US [patent_app_date] => 2024-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18664035 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/664035
Neural networks for embedded devices May 13, 2024 Issued
Array ( [id] => 20351460 [patent_doc_number] => 20250348312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-13 [patent_title] => INTERCONNECT STRUCTURES FOR CONFIGURABLE CPU PIPELINES [patent_app_type] => utility [patent_app_number] => 18/656836 [patent_app_country] => US [patent_app_date] => 2024-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11705 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18656836 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/656836
INTERCONNECT STRUCTURES FOR CONFIGURABLE CPU PIPELINES May 6, 2024 Pending
Array ( [id] => 19391408 [patent_doc_number] => 20240281278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => PIPELINE ARBITRATION [patent_app_type] => utility [patent_app_number] => 18/654035 [patent_app_country] => US [patent_app_date] => 2024-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17694 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18654035 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/654035
Pipeline arbitration May 2, 2024 Issued
Array ( [id] => 19686171 [patent_doc_number] => 20250004716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => SYSTEMS, METHODS, AND APPARATUSES FOR TILE LOAD [patent_app_type] => utility [patent_app_number] => 18/654951 [patent_app_country] => US [patent_app_date] => 2024-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19107 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18654951 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/654951
SYSTEMS, METHODS, AND APPARATUSES FOR TILE LOAD May 2, 2024 Pending
Array ( [id] => 19558951 [patent_doc_number] => 20240370743 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => NEURAL NETWORK DATA COMPUTATION USING MIXED-PRECISION [patent_app_type] => utility [patent_app_number] => 18/650612 [patent_app_country] => US [patent_app_date] => 2024-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13006 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18650612 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/650612
Neural network data computation using mixed-precision Apr 29, 2024 Issued
Array ( [id] => 19506933 [patent_doc_number] => 12118356 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-10-15 [patent_title] => Multi-threading processor and operating method thereof [patent_app_type] => utility [patent_app_number] => 18/643178 [patent_app_country] => US [patent_app_date] => 2024-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6357 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18643178 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/643178
Multi-threading processor and operating method thereof Apr 22, 2024 Issued
Array ( [id] => 19864552 [patent_doc_number] => 20250103338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => Processor Operand Management Using Fusion Buffer [patent_app_type] => utility [patent_app_number] => 18/628403 [patent_app_country] => US [patent_app_date] => 2024-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24873 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18628403 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/628403
Processor operand management using fusion buffer Apr 4, 2024 Issued
Array ( [id] => 19334290 [patent_doc_number] => 20240248720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => INSTRUCTIONS TO CONVERT FROM FP16 TO BF8 [patent_app_type] => utility [patent_app_number] => 18/627907 [patent_app_country] => US [patent_app_date] => 2024-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14338 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18627907 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/627907
Instructions to convert from FP16 to BF8 Apr 4, 2024 Issued
Array ( [id] => 19538603 [patent_doc_number] => 12131156 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-10-29 [patent_title] => Manycore system for performing execution of multi-threads in asynchronous manner [patent_app_type] => utility [patent_app_number] => 18/626753 [patent_app_country] => US [patent_app_date] => 2024-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7181 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 325 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18626753 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/626753
Manycore system for performing execution of multi-threads in asynchronous manner Apr 3, 2024 Issued
Array ( [id] => 19347670 [patent_doc_number] => 20240256633 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => APPLICATION PROGRAMMING INTERFACE TO ACCELERATE MATRIX OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/620228 [patent_app_country] => US [patent_app_date] => 2024-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 50211 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18620228 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/620228
Application programming interface to accelerate matrix operations Mar 27, 2024 Issued
Array ( [id] => 19283787 [patent_doc_number] => 20240220263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => CONDITIONAL EXECUTION SPECIFICATION OF INSTRUCTIONS USING CONDITIONAL EXTENSION SLOTS IN THE SAME EXECUTE PACKET IN A VLIW PROCESSOR [patent_app_type] => utility [patent_app_number] => 18/609622 [patent_app_country] => US [patent_app_date] => 2024-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10595 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18609622 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/609622
Conditional execution specification of instructions using conditional extension slots in the same execute packet in a VLIW processor Mar 18, 2024 Issued
Array ( [id] => 20481820 [patent_doc_number] => 12530295 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-20 [patent_title] => Decoupling atomicity from operation size [patent_app_type] => utility [patent_app_number] => 18/587289 [patent_app_country] => US [patent_app_date] => 2024-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3779 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18587289 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/587289
Decoupling atomicity from operation size Feb 25, 2024 Issued
Array ( [id] => 20454776 [patent_doc_number] => 12517830 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-06 [patent_title] => Write streaming with cache write acknowledgment in a processor [patent_app_type] => utility [patent_app_number] => 18/425165 [patent_app_country] => US [patent_app_date] => 2024-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18425165 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/425165
Write streaming with cache write acknowledgment in a processor Jan 28, 2024 Issued
Array ( [id] => 20137966 [patent_doc_number] => 20250245010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => RETURN ADDRESS RESTORATION [patent_app_type] => utility [patent_app_number] => 18/425239 [patent_app_country] => US [patent_app_date] => 2024-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8147 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18425239 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/425239
Return address restoration Jan 28, 2024 Issued
Menu