Search

Steven G. Snyder

Examiner (ID: 7148, Phone: (571)270-1971 , Office: P/2184 )

Most Active Art Unit
2184
Art Unit(s)
2184
Total Applications
1026
Issued Applications
801
Pending Applications
59
Abandoned Applications
180

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20137965 [patent_doc_number] => 20250245009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => Systems and Methods for Monitoring an Instruction Bus [patent_app_type] => utility [patent_app_number] => 18/423049 [patent_app_country] => US [patent_app_date] => 2024-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1195 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18423049 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/423049
Systems and methods for monitoring an instruction bus Jan 24, 2024 Issued
Array ( [id] => 19267559 [patent_doc_number] => 20240211262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => APPARATUSES, METHODS, AND SYSTEMS TO ACCELERATE STORE PROCESSING [patent_app_type] => utility [patent_app_number] => 18/419059 [patent_app_country] => US [patent_app_date] => 2024-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19924 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18419059 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/419059
Apparatuses, methods, and systems toprecisely monitor memory store accesses Jan 21, 2024 Issued
Array ( [id] => 20096689 [patent_doc_number] => 20250226625 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => SHARED CONDUCTOR FOR SIGNALS DIFFERING IN FREQUENCY [patent_app_type] => utility [patent_app_number] => 18/409616 [patent_app_country] => US [patent_app_date] => 2024-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7472 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18409616 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/409616
SHARED CONDUCTOR FOR SIGNALS DIFFERING IN FREQUENCY Jan 9, 2024 Pending
Array ( [id] => 19174498 [patent_doc_number] => 20240160472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => SCHEDULING TASKS USING WORK FULLNESS COUNTER [patent_app_type] => utility [patent_app_number] => 18/406807 [patent_app_country] => US [patent_app_date] => 2024-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16242 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18406807 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/406807
Scheduling tasks using work fullness counter Jan 7, 2024 Issued
Array ( [id] => 19992572 [patent_doc_number] => 20250130794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => MULTI-FORMAT OPERAND CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/399659 [patent_app_country] => US [patent_app_date] => 2023-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1135 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18399659 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/399659
MULTI-FORMAT OPERAND CIRCUIT Dec 27, 2023 Pending
Array ( [id] => 19603182 [patent_doc_number] => 20240394062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => Processor having Switch Instruction Circuit [patent_app_type] => utility [patent_app_number] => 18/534203 [patent_app_country] => US [patent_app_date] => 2023-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9353 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18534203 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/534203
Processor having switch instruction circuit Dec 7, 2023 Issued
Array ( [id] => 19934049 [patent_doc_number] => 12307254 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Systems and methods for handling macro compatibility for documents at a storage system [patent_app_type] => utility [patent_app_number] => 18/520375 [patent_app_country] => US [patent_app_date] => 2023-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 5801 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18520375 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/520375
Systems and methods for handling macro compatibility for documents at a storage system Nov 26, 2023 Issued
Array ( [id] => 19942550 [patent_doc_number] => 12314682 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Floating point adder [patent_app_type] => utility [patent_app_number] => 18/518972 [patent_app_country] => US [patent_app_date] => 2023-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 7092 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18518972 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/518972
Floating point adder Nov 24, 2023 Issued
Array ( [id] => 19036676 [patent_doc_number] => 20240086491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => APPLICATION PROGRAMMING INTERFACE TO ACCELERATE MATRIX OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/515062 [patent_app_country] => US [patent_app_date] => 2023-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 50209 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18515062 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/515062
Application programming interface to accelerate matrix operations Nov 19, 2023 Issued
Array ( [id] => 20434309 [patent_doc_number] => 12505053 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-23 [patent_title] => Method for supporting erasure code data protection with embedded PCIe switch inside FPGA+SSD [patent_app_type] => utility [patent_app_number] => 18/513610 [patent_app_country] => US [patent_app_date] => 2023-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 23180 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18513610 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/513610
Method for supporting erasure code data protection with embedded PCIe switch inside FPGA+SSD Nov 18, 2023 Issued
Array ( [id] => 19174625 [patent_doc_number] => 20240160599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => SERIAL-BUS SYSTEM WITH DYNAMIC ADDRESS TABLE AND METHOD FOR CONTROLLING THE SAME [patent_app_type] => utility [patent_app_number] => 18/384395 [patent_app_country] => US [patent_app_date] => 2023-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3315 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18384395 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/384395
SERIAL-BUS SYSTEM WITH DYNAMIC ADDRESS TABLE AND METHOD FOR CONTROLLING THE SAME Oct 26, 2023 Pending
Array ( [id] => 19718944 [patent_doc_number] => 12204481 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Configurable logic platform [patent_app_type] => utility [patent_app_number] => 18/383833 [patent_app_country] => US [patent_app_date] => 2023-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 15799 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18383833 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/383833
Configurable logic platform Oct 24, 2023 Issued
Array ( [id] => 19718944 [patent_doc_number] => 12204481 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Configurable logic platform [patent_app_type] => utility [patent_app_number] => 18/383833 [patent_app_country] => US [patent_app_date] => 2023-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 15799 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18383833 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/383833
Configurable logic platform Oct 24, 2023 Issued
Array ( [id] => 19009227 [patent_doc_number] => 20240073298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => INTELLIGENT SCHEDULING APPARATUS AND METHOD [patent_app_type] => utility [patent_app_number] => 18/492968 [patent_app_country] => US [patent_app_date] => 2023-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7561 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18492968 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/492968
Intelligent scheduling apparatus and method Oct 23, 2023 Issued
Array ( [id] => 19992579 [patent_doc_number] => 20250130801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => PROCESSING UNIT EMPLOYING MICRO-OPERATIONS (MICRO-OPS) RANDOM ACCESS MEMORY (RAM) AS MAIN PROGRAM MEMORY [patent_app_type] => utility [patent_app_number] => 18/491455 [patent_app_country] => US [patent_app_date] => 2023-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4590 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18491455 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/491455
Processing unit employing micro-operations (micro-ops) random access memory (RAM) as main program memory Oct 19, 2023 Issued
Array ( [id] => 19992576 [patent_doc_number] => 20250130798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => PROVIDING ADDITIONAL OPERATIONS FOR A FUNCTIONAL UNIT OF A PROCESSOR CORE [patent_app_type] => utility [patent_app_number] => 18/490628 [patent_app_country] => US [patent_app_date] => 2023-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18490628 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/490628
Providing additional operations for a functional unit of a processor core Oct 18, 2023 Issued
Array ( [id] => 19979219 [patent_doc_number] => 12346696 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-01 [patent_title] => System and method of digital to analog conversion using dynamic element matching [patent_app_type] => utility [patent_app_number] => 18/483064 [patent_app_country] => US [patent_app_date] => 2023-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 3837 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18483064 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/483064
System and method of digital to analog conversion using dynamic element matching Oct 8, 2023 Issued
Array ( [id] => 19219747 [patent_doc_number] => 20240184451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => APPARATUSES AND METHODS FOR ENCODING AND DECODING OF SIGNAL LINES FOR MULTI-LEVEL COMMUNICATION ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 18/479642 [patent_app_country] => US [patent_app_date] => 2023-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12061 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18479642 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/479642
APPARATUSES AND METHODS FOR ENCODING AND DECODING OF SIGNAL LINES FOR MULTI-LEVEL COMMUNICATION ARCHITECTURES Oct 1, 2023 Pending
Array ( [id] => 19334282 [patent_doc_number] => 20240248712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => MASK PATTERNS GENERATED IN MEMORY FROM SEED VECTORS [patent_app_type] => utility [patent_app_number] => 18/476938 [patent_app_country] => US [patent_app_date] => 2023-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17573 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18476938 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/476938
MASK PATTERNS GENERATED IN MEMORY FROM SEED VECTORS Sep 27, 2023 Pending
Array ( [id] => 20228446 [patent_doc_number] => 12417098 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-16 [patent_title] => Data processing method and apparatus, and related product for increased efficiency of tensor processing [patent_app_type] => utility [patent_app_number] => 18/374176 [patent_app_country] => US [patent_app_date] => 2023-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3819 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18374176 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/374176
Data processing method and apparatus, and related product for increased efficiency of tensor processing Sep 27, 2023 Issued
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