
Steven G. Snyder
Examiner (ID: 7148, Phone: (571)270-1971 , Office: P/2184 )
| Most Active Art Unit | 2184 |
| Art Unit(s) | 2184 |
| Total Applications | 1026 |
| Issued Applications | 801 |
| Pending Applications | 59 |
| Abandoned Applications | 180 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18154784
[patent_doc_number] => 11567762
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2023-01-31
[patent_title] => Streaming execution for a quantum processing system
[patent_app_type] => utility
[patent_app_number] => 17/541044
[patent_app_country] => US
[patent_app_date] => 2021-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 8663
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17541044
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/541044 | Streaming execution for a quantum processing system | Dec 1, 2021 | Issued |
Array
(
[id] => 18527658
[patent_doc_number] => 11714649
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-08-01
[patent_title] => RISC-V-based 3D interconnected multi-core processor architecture and working method thereof
[patent_app_type] => utility
[patent_app_number] => 17/621600
[patent_app_country] => US
[patent_app_date] => 2021-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 5171
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17621600
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/621600 | RISC-V-based 3D interconnected multi-core processor architecture and working method thereof | Nov 30, 2021 | Issued |
Array
(
[id] => 17462347
[patent_doc_number] => 20220075652
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-10
[patent_title] => SCHEDULING TASKS USING WORK FULLNESS COUNTER
[patent_app_type] => utility
[patent_app_number] => 17/529004
[patent_app_country] => US
[patent_app_date] => 2021-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16206
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17529004
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/529004 | Scheduling tasks using work fullness counter | Nov 16, 2021 | Issued |
Array
(
[id] => 17462316
[patent_doc_number] => 20220075621
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-10
[patent_title] => 22 RESOURCE ALLOCATION IN A MULTI-PROCESSOR SYSTEM
[patent_app_type] => utility
[patent_app_number] => 17/527288
[patent_app_country] => US
[patent_app_date] => 2021-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4977
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17527288
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/527288 | Resource allocation in a multi-processor system | Nov 15, 2021 | Issued |
Array
(
[id] => 19711192
[patent_doc_number] => 20250021334
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-16
[patent_title] => METHOD FOR EXECUTION OF BUS CONTROLLER, COMPUTER DEVICE AND STORAGE MEDIUM
[patent_app_type] => utility
[patent_app_number] => 18/713160
[patent_app_country] => US
[patent_app_date] => 2021-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10377
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18713160
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/713160 | Method for execution of bus controller, computer device and storage medium | Oct 19, 2021 | Issued |
Array
(
[id] => 18079608
[patent_doc_number] => 20220405220
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-22
[patent_title] => INTERCONNECT LAYER SEND QUEUE RESERVATION SYSTEM
[patent_app_type] => utility
[patent_app_number] => 17/502397
[patent_app_country] => US
[patent_app_date] => 2021-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8466
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17502397
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/502397 | INTERCONNECT LAYER SEND QUEUE RESERVATION SYSTEM | Oct 14, 2021 | Pending |
Array
(
[id] => 18838852
[patent_doc_number] => 11846922
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-12-19
[patent_title] => Method and system for clearing register by PLD, device, and medium
[patent_app_type] => utility
[patent_app_number] => 18/036597
[patent_app_country] => US
[patent_app_date] => 2021-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 5214
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18036597
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/036597 | Method and system for clearing register by PLD, device, and medium | Sep 29, 2021 | Issued |
Array
(
[id] => 17345724
[patent_doc_number] => 20220012055
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-01-13
[patent_title] => APPARATUS, COMPUTER-READABLE MEDIUM, AND METHOD FOR REDUCING BOUNDS CHECKING OVERHEAD BY INSTRUMENTING POINTER ARITHMETIC
[patent_app_type] => utility
[patent_app_number] => 17/485347
[patent_app_country] => US
[patent_app_date] => 2021-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15788
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17485347
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/485347 | Apparatus, computer-readable medium, and method for reducing bounds checking overhead by instrumenting pointer arithmetic | Sep 24, 2021 | Issued |
Array
(
[id] => 19523123
[patent_doc_number] => 12124853
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-10-22
[patent_title] => Data loading and storage system and method
[patent_app_type] => utility
[patent_app_number] => 17/484850
[patent_app_country] => US
[patent_app_date] => 2021-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 5363
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17484850
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/484850 | Data loading and storage system and method | Sep 23, 2021 | Issued |
Array
(
[id] => 18287734
[patent_doc_number] => 20230103206
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-30
[patent_title] => CACHING BASED ON BRANCH INSTRUCTIONS IN A PROCESSOR
[patent_app_type] => utility
[patent_app_number] => 17/448806
[patent_app_country] => US
[patent_app_date] => 2021-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 28674
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17448806
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/448806 | CACHING BASED ON BRANCH INSTRUCTIONS IN A PROCESSOR | Sep 23, 2021 | Abandoned |
Array
(
[id] => 19243370
[patent_doc_number] => 12013809
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-06-18
[patent_title] => Computing array and processor having the same
[patent_app_type] => utility
[patent_app_number] => 17/483395
[patent_app_country] => US
[patent_app_date] => 2021-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 4166
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 280
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17483395
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/483395 | Computing array and processor having the same | Sep 22, 2021 | Issued |
Array
(
[id] => 18386090
[patent_doc_number] => 11656871
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-05-23
[patent_title] => Handling an input/output store instruction
[patent_app_type] => utility
[patent_app_number] => 17/480337
[patent_app_country] => US
[patent_app_date] => 2021-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 8040
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17480337
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/480337 | Handling an input/output store instruction | Sep 20, 2021 | Issued |
Array
(
[id] => 18386090
[patent_doc_number] => 11656871
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-05-23
[patent_title] => Handling an input/output store instruction
[patent_app_type] => utility
[patent_app_number] => 17/480337
[patent_app_country] => US
[patent_app_date] => 2021-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 8040
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17480337
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/480337 | Handling an input/output store instruction | Sep 20, 2021 | Issued |
Array
(
[id] => 18386090
[patent_doc_number] => 11656871
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-05-23
[patent_title] => Handling an input/output store instruction
[patent_app_type] => utility
[patent_app_number] => 17/480337
[patent_app_country] => US
[patent_app_date] => 2021-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 8040
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17480337
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/480337 | Handling an input/output store instruction | Sep 20, 2021 | Issued |
Array
(
[id] => 18386090
[patent_doc_number] => 11656871
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-05-23
[patent_title] => Handling an input/output store instruction
[patent_app_type] => utility
[patent_app_number] => 17/480337
[patent_app_country] => US
[patent_app_date] => 2021-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 8040
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17480337
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/480337 | Handling an input/output store instruction | Sep 20, 2021 | Issued |
Array
(
[id] => 17316979
[patent_doc_number] => 20210406028
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-30
[patent_title] => Systems and Methods for Policy Execution Processing
[patent_app_type] => utility
[patent_app_number] => 17/474830
[patent_app_country] => US
[patent_app_date] => 2021-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13390
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 204
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17474830
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/474830 | Systems and methods for policy execution processing | Sep 13, 2021 | Issued |
Array
(
[id] => 17316972
[patent_doc_number] => 20210406021
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-30
[patent_title] => DUAL DATA STREAMS SHARING DUAL LEVEL TWO CACHE ACCESS PORTS TO MAXIMIZE BANDWIDTH UTILIZATION
[patent_app_type] => utility
[patent_app_number] => 17/472852
[patent_app_country] => US
[patent_app_date] => 2021-09-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 18862
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17472852
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/472852 | Dual data streams sharing dual level two cache access ports to maximize bandwidth utilization | Sep 12, 2021 | Issued |
Array
(
[id] => 20758266
[patent_doc_number] => 12651037
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-06-09
[patent_title] => Application programming interface to accelerate matrix operations
[patent_app_type] => utility
[patent_app_number] => 17/471126
[patent_app_country] => US
[patent_app_date] => 2021-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 44
[patent_figures_cnt] => 44
[patent_no_of_words] => 45283
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17471126
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/471126 | Application programming interface to accelerate matrix operations | Sep 8, 2021 | Issued |
Array
(
[id] => 17316964
[patent_doc_number] => 20210406013
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-30
[patent_title] => PROCESSING DEVICE, INFORMATION PROCESSING DEVICE, AND INFORMATION PROCESSING METHOD
[patent_app_type] => utility
[patent_app_number] => 17/468914
[patent_app_country] => US
[patent_app_date] => 2021-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7945
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17468914
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/468914 | PROCESSING DEVICE, INFORMATION PROCESSING DEVICE, AND INFORMATION PROCESSING METHOD | Sep 7, 2021 | Abandoned |
Array
(
[id] => 18578017
[patent_doc_number] => 11734550
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-08-22
[patent_title] => Discrete three-dimensional processor
[patent_app_type] => utility
[patent_app_number] => 17/467436
[patent_app_country] => US
[patent_app_date] => 2021-09-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 56
[patent_no_of_words] => 20794
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17467436
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/467436 | Discrete three-dimensional processor | Sep 5, 2021 | Issued |