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Steven H. Whitesell Gordon

Examiner (ID: 3426, Phone: (571)270-3942 , Office: P/2882 )

Most Active Art Unit
1759
Art Unit(s)
1759
Total Applications
2
Issued Applications
0
Pending Applications
2
Abandoned Applications
0

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18113145 [patent_doc_number] => 20230006025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => DISPLAY APPARATUS [patent_app_type] => utility [patent_app_number] => 17/851444 [patent_app_country] => US [patent_app_date] => 2022-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18632 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17851444 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/851444
Display apparatus Jun 27, 2022 Issued
Array ( [id] => 18097571 [patent_doc_number] => 20220415912 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => STACKED STRUCTURE, MEMORY DEVICE AND METHOD OF MANUFACTURING STACKED STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/851178 [patent_app_country] => US [patent_app_date] => 2022-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2833 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17851178 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/851178
STACKED STRUCTURE, MEMORY DEVICE AND METHOD OF MANUFACTURING STACKED STRUCTURE Jun 27, 2022 Pending
Array ( [id] => 20496737 [patent_doc_number] => 12538628 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-27 [patent_title] => Flexible display device [patent_app_type] => utility [patent_app_number] => 17/842741 [patent_app_country] => US [patent_app_date] => 2022-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 1105 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17842741 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/842741
Flexible display device Jun 15, 2022 Issued
Array ( [id] => 20443089 [patent_doc_number] => 12513935 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-30 [patent_title] => III-V semiconductor device [patent_app_type] => utility [patent_app_number] => 17/837719 [patent_app_country] => US [patent_app_date] => 2022-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1188 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17837719 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/837719
III-V semiconductor device Jun 9, 2022 Issued
Array ( [id] => 18068158 [patent_doc_number] => 20220399246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-15 [patent_title] => ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/829533 [patent_app_country] => US [patent_app_date] => 2022-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3442 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17829533 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/829533
Electronic package of two vertically stacked chips with chip-to-chip bump connections and manufacturing method thereof May 31, 2022 Issued
Array ( [id] => 19436056 [patent_doc_number] => 20240304554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 18/275312 [patent_app_country] => US [patent_app_date] => 2022-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18566 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18275312 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/275312
SEMICONDUCTOR PACKAGE Jan 27, 2022 Pending
Array ( [id] => 19023360 [patent_doc_number] => 20240079531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => OPTOELECTRONIC SEMICONDUCTOR COMPONENT, OPTOELECTRONIC DEVICE, AND METHOD FOR PRODUCING AN OPTOELECTRONIC SEMICONDUCTOR COMPONENT AND/OR OPTOELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/272074 [patent_app_country] => US [patent_app_date] => 2021-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7502 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18272074 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/272074
OPTOELECTRONIC SEMICONDUCTOR COMPONENT, OPTOELECTRONIC DEVICE, AND METHOD FOR PRODUCING AN OPTOELECTRONIC SEMICONDUCTOR COMPONENT AND/OR OPTOELECTRONIC DEVICE Dec 21, 2021 Pending
Array ( [id] => 19086189 [patent_doc_number] => 20240112990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR APPARATUS [patent_app_type] => utility [patent_app_number] => 18/249473 [patent_app_country] => US [patent_app_date] => 2021-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26064 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18249473 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/249473
METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR APPARATUS Dec 13, 2021 Pending
Array ( [id] => 18440112 [patent_doc_number] => 20230187407 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => FINE-GRAINED DISAGGREGATED SERVER ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 17/548304 [patent_app_country] => US [patent_app_date] => 2021-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 32764 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17548304 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/548304
Fine-grained disaggregated server architecture Dec 9, 2021 Issued
Array ( [id] => 20416912 [patent_doc_number] => 12500207 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-16 [patent_title] => Packaging architecture with intermediate routing layers [patent_app_type] => utility [patent_app_number] => 17/543419 [patent_app_country] => US [patent_app_date] => 2021-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 10038 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17543419 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/543419
Packaging architecture with intermediate routing layers Dec 5, 2021 Issued
Array ( [id] => 18345374 [patent_doc_number] => 20230133484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => INTERCONNECTS WITH LINER THAT RESONATES DURING MICROWAVE ANNEAL [patent_app_type] => utility [patent_app_number] => 17/452803 [patent_app_country] => US [patent_app_date] => 2021-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8859 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17452803 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/452803
INTERCONNECTS WITH LINER THAT RESONATES DURING MICROWAVE ANNEAL Oct 28, 2021 Abandoned
Array ( [id] => 18270271 [patent_doc_number] => 20230091513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => WAFER-LEVEL CHIP STRUCTURE, MULTIPLE-CHIP STACKED AND INTERCONNECTED STRUCTURE AND FABRICATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/908118 [patent_app_country] => US [patent_app_date] => 2021-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4857 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17908118 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/908118
WAFER-LEVEL CHIP STRUCTURE, MULTIPLE-CHIP STACKED AND INTERCONNECTED STRUCTURE AND FABRICATING METHOD THEREOF Mar 4, 2021 Pending
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