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Steven Ho Yin Loke

Supervisory Patent Examiner (ID: 5565, Phone: (571)272-1657 , Office: P/2818 )

Most Active Art Unit
2508
Art Unit(s)
2818, 2815, 2811, 2508
Total Applications
1288
Issued Applications
941
Pending Applications
39
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3627385 [patent_doc_number] => 05612547 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-18 [patent_title] => 'Silicon carbide static induction transistor' [patent_app_type] => 1 [patent_app_number] => 8/462405 [patent_app_country] => US [patent_app_date] => 1995-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 15 [patent_no_of_words] => 4263 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/612/05612547.pdf [firstpage_image] =>[orig_patent_app_number] => 462405 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/462405
Silicon carbide static induction transistor Jun 4, 1995 Issued
Array ( [id] => 3728187 [patent_doc_number] => 05672897 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-30 [patent_title] => 'Bimos semiconductor integrated circuit device including high speed vertical bipolar transistors' [patent_app_type] => 1 [patent_app_number] => 8/462902 [patent_app_country] => US [patent_app_date] => 1995-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 55 [patent_no_of_words] => 9482 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/672/05672897.pdf [firstpage_image] =>[orig_patent_app_number] => 462902 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/462902
Bimos semiconductor integrated circuit device including high speed vertical bipolar transistors Jun 4, 1995 Issued
Array ( [id] => 3953664 [patent_doc_number] => 05977586 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Non-volatile integrated low-doped drain device with partially overlapping gate regions' [patent_app_type] => 1 [patent_app_number] => 8/455570 [patent_app_country] => US [patent_app_date] => 1995-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3034 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/977/05977586.pdf [firstpage_image] =>[orig_patent_app_number] => 455570 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/455570
Non-volatile integrated low-doped drain device with partially overlapping gate regions May 30, 1995 Issued
08/455574 INSULATING FILM FORMED USING AN ORGANIC SILANE AND METHOD OF PRODUCING SEMICONDUCTOR DEVICE May 30, 1995 Abandoned
Array ( [id] => 3668653 [patent_doc_number] => 05668385 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-16 [patent_title] => 'Power semiconductor component with transparent emitter and stop layer' [patent_app_type] => 1 [patent_app_number] => 8/453674 [patent_app_country] => US [patent_app_date] => 1995-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3588 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/668/05668385.pdf [firstpage_image] =>[orig_patent_app_number] => 453674 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/453674
Power semiconductor component with transparent emitter and stop layer May 29, 1995 Issued
08/488558 DEVICE INCLUDING HAVING A NONVOLATILE MEMORY HAVING WRITE, ERASE AND READ MODES May 29, 1995 Abandoned
Array ( [id] => 3707125 [patent_doc_number] => 05675169 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-07 [patent_title] => 'Motor driving circuit with surge detection/protection and its structure in a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/451750 [patent_app_country] => US [patent_app_date] => 1995-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 6843 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/675/05675169.pdf [firstpage_image] =>[orig_patent_app_number] => 451750 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/451750
Motor driving circuit with surge detection/protection and its structure in a semiconductor device May 25, 1995 Issued
Array ( [id] => 3775668 [patent_doc_number] => 05773846 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Transistor and process for fabricating the same' [patent_app_type] => 1 [patent_app_number] => 8/449669 [patent_app_country] => US [patent_app_date] => 1995-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 20 [patent_no_of_words] => 6056 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/773/05773846.pdf [firstpage_image] =>[orig_patent_app_number] => 449669 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/449669
Transistor and process for fabricating the same May 23, 1995 Issued
Array ( [id] => 3857420 [patent_doc_number] => 05767547 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'High voltage thin film transistor having a linear doping profile' [patent_app_type] => 1 [patent_app_number] => 8/448268 [patent_app_country] => US [patent_app_date] => 1995-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 3559 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 366 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/767/05767547.pdf [firstpage_image] =>[orig_patent_app_number] => 448268 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/448268
High voltage thin film transistor having a linear doping profile May 22, 1995 Issued
Array ( [id] => 3520162 [patent_doc_number] => 05576570 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-19 [patent_title] => 'Semiconductor device having CMOS circuit' [patent_app_type] => 1 [patent_app_number] => 8/438366 [patent_app_country] => US [patent_app_date] => 1995-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3498 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 327 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/576/05576570.pdf [firstpage_image] =>[orig_patent_app_number] => 438366 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/438366
Semiconductor device having CMOS circuit May 9, 1995 Issued
Array ( [id] => 3692340 [patent_doc_number] => 05696391 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-09 [patent_title] => 'Overload protection circuit' [patent_app_type] => 1 [patent_app_number] => 8/435642 [patent_app_country] => US [patent_app_date] => 1995-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 4554 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/696/05696391.pdf [firstpage_image] =>[orig_patent_app_number] => 435642 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/435642
Overload protection circuit May 4, 1995 Issued
Array ( [id] => 677088 [patent_doc_number] => 07087962 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-08-08 [patent_title] => 'Method for forming a MOS transistor having lightly dopped drain regions and structure thereof' [patent_app_type] => utility [patent_app_number] => 08/433561 [patent_app_country] => US [patent_app_date] => 1995-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 4 [patent_no_of_words] => 4010 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/087/07087962.pdf [firstpage_image] =>[orig_patent_app_number] => 08433561 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/433561
Method for forming a MOS transistor having lightly dopped drain regions and structure thereof May 2, 1995 Issued
Array ( [id] => 3815810 [patent_doc_number] => 05811860 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Bi-CMOS merged devices' [patent_app_type] => 1 [patent_app_number] => 8/431232 [patent_app_country] => US [patent_app_date] => 1995-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 1970 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/811/05811860.pdf [firstpage_image] =>[orig_patent_app_number] => 431232 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/431232
Bi-CMOS merged devices Apr 27, 1995 Issued
Array ( [id] => 3732987 [patent_doc_number] => 05670811 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-23 [patent_title] => 'Vertical insulated gate semiconductor device having high current density and high reliability' [patent_app_type] => 1 [patent_app_number] => 8/430289 [patent_app_country] => US [patent_app_date] => 1995-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 19 [patent_no_of_words] => 3612 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 417 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/670/05670811.pdf [firstpage_image] =>[orig_patent_app_number] => 430289 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/430289
Vertical insulated gate semiconductor device having high current density and high reliability Apr 27, 1995 Issued
Array ( [id] => 3692189 [patent_doc_number] => 05691550 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-25 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 8/430287 [patent_app_country] => US [patent_app_date] => 1995-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 28 [patent_no_of_words] => 5317 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 368 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/691/05691550.pdf [firstpage_image] =>[orig_patent_app_number] => 430287 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/430287
Semiconductor device and method of manufacturing the same Apr 27, 1995 Issued
08/429438 SEMICONDUCTOR DEVICE HAVING A VERTICAL INSULATED GATE FIELD EFFECT DEVICE AND A BREAKDOWN REGION REMOTE FROM THE GATE Apr 26, 1995 Abandoned
Array ( [id] => 3699202 [patent_doc_number] => 05619055 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-08 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 8/429882 [patent_app_country] => US [patent_app_date] => 1995-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 25 [patent_no_of_words] => 7325 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 299 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/619/05619055.pdf [firstpage_image] =>[orig_patent_app_number] => 429882 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/429882
Semiconductor integrated circuit device Apr 26, 1995 Issued
08/428752 CO-IMPLANTATION OF ARSENIC AND PHOSPHORUS IN EXTENDED DRAIN REGION FOR IMPROVED PERFORMANCE OF HIGH VOLTAGE NMOS DEVICE Apr 24, 1995 Abandoned
Array ( [id] => 3594605 [patent_doc_number] => 05567969 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-22 [patent_title] => 'Compound modulated integrated transistor structure with reduced bipolar switch back effect' [patent_app_type] => 1 [patent_app_number] => 8/425173 [patent_app_country] => US [patent_app_date] => 1995-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 1831 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/567/05567969.pdf [firstpage_image] =>[orig_patent_app_number] => 425173 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/425173
Compound modulated integrated transistor structure with reduced bipolar switch back effect Apr 19, 1995 Issued
Array ( [id] => 3616414 [patent_doc_number] => 05565700 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-15 [patent_title] => 'Surface counter doped N-LDD for high carrier reliability' [patent_app_type] => 1 [patent_app_number] => 8/426491 [patent_app_country] => US [patent_app_date] => 1995-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3149 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/565/05565700.pdf [firstpage_image] =>[orig_patent_app_number] => 426491 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/426491
Surface counter doped N-LDD for high carrier reliability Apr 19, 1995 Issued
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