| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3529448
[patent_doc_number] => 05504359
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-02
[patent_title] => 'Vertical FET device with low gate to source overlap capacitance'
[patent_app_type] => 1
[patent_app_number] => 8/369851
[patent_app_country] => US
[patent_app_date] => 1995-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 11
[patent_no_of_words] => 2203
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[pdf_file] => patents/05/504/05504359.pdf
[firstpage_image] =>[orig_patent_app_number] => 369851
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/369851 | Vertical FET device with low gate to source overlap capacitance | Jan 5, 1995 | Issued |
| 08/369049 | FIELD IMPLANT FOR SILICON CONTROLLED RECTIFIER | Jan 4, 1995 | Abandoned |
Array
(
[id] => 3554263
[patent_doc_number] => 05572046
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-05
[patent_title] => 'Semiconductor device having at least two thin film transistors'
[patent_app_type] => 1
[patent_app_number] => 8/365744
[patent_app_country] => US
[patent_app_date] => 1994-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 10
[patent_no_of_words] => 7914
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[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/572/05572046.pdf
[firstpage_image] =>[orig_patent_app_number] => 365744
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/365744 | Semiconductor device having at least two thin film transistors | Dec 28, 1994 | Issued |
| 08/365593 | SEMICONDUCTOR INTEGRATED CIRCUIT | Dec 27, 1994 | Abandoned |
Array
(
[id] => 3595974
[patent_doc_number] => 05521415
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-05-28
[patent_title] => 'Semiconductor device having a circuit for protecting the device from electrostatic discharge'
[patent_app_type] => 1
[patent_app_number] => 8/361134
[patent_app_country] => US
[patent_app_date] => 1994-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 3727
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/521/05521415.pdf
[firstpage_image] =>[orig_patent_app_number] => 361134
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/361134 | Semiconductor device having a circuit for protecting the device from electrostatic discharge | Dec 20, 1994 | Issued |
| 08/360978 | ISOLATION BY ACTIVE TRANSISTORS WITH GROUNDED GATES | Dec 19, 1994 | Abandoned |
Array
(
[id] => 3672099
[patent_doc_number] => 05600177
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-04
[patent_title] => 'Semiconductor device having an electrically conductive layer including a polycrystalline layer containing an impurity and a metallic silicide layer'
[patent_app_type] => 1
[patent_app_number] => 8/358456
[patent_app_country] => US
[patent_app_date] => 1994-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 11
[patent_no_of_words] => 4046
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/600/05600177.pdf
[firstpage_image] =>[orig_patent_app_number] => 358456
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/358456 | Semiconductor device having an electrically conductive layer including a polycrystalline layer containing an impurity and a metallic silicide layer | Dec 18, 1994 | Issued |
Array
(
[id] => 3579849
[patent_doc_number] => 05523614
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-06-04
[patent_title] => 'Bipolar transistor having enhanced high speed operation through reduced base leakage current'
[patent_app_type] => 1
[patent_app_number] => 8/357215
[patent_app_country] => US
[patent_app_date] => 1994-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 3506
[patent_no_of_claims] => 5
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/523/05523614.pdf
[firstpage_image] =>[orig_patent_app_number] => 357215
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/357215 | Bipolar transistor having enhanced high speed operation through reduced base leakage current | Dec 12, 1994 | Issued |
Array
(
[id] => 3585602
[patent_doc_number] => 05498889
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-03-12
[patent_title] => 'Semiconductor device having increased capacitance and method for making the same'
[patent_app_type] => 1
[patent_app_number] => 8/353737
[patent_app_country] => US
[patent_app_date] => 1994-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 3438
[patent_no_of_claims] => 10
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/498/05498889.pdf
[firstpage_image] =>[orig_patent_app_number] => 353737
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/353737 | Semiconductor device having increased capacitance and method for making the same | Dec 11, 1994 | Issued |
Array
(
[id] => 3654165
[patent_doc_number] => 05606183
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-25
[patent_title] => 'Double-gated turn-off thyristor'
[patent_app_type] => 1
[patent_app_number] => 8/352956
[patent_app_country] => US
[patent_app_date] => 1994-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 3395
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 242
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/606/05606183.pdf
[firstpage_image] =>[orig_patent_app_number] => 352956
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/352956 | Double-gated turn-off thyristor | Dec 8, 1994 | Issued |
Array
(
[id] => 3698556
[patent_doc_number] => 05661329
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-26
[patent_title] => 'Semiconductor integrated circuit device including an improved separating groove arrangement'
[patent_app_type] => 1
[patent_app_number] => 8/350944
[patent_app_country] => US
[patent_app_date] => 1994-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 22
[patent_no_of_words] => 8365
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 284
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/661/05661329.pdf
[firstpage_image] =>[orig_patent_app_number] => 350944
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/350944 | Semiconductor integrated circuit device including an improved separating groove arrangement | Dec 6, 1994 | Issued |
| 08/347998 | TUNNEL DIODE LAYOUT FOR AN EEPROM CELL FOR PROTECTING THE TUNNEL DIODE REGION | Dec 4, 1994 | Abandoned |
| 08/347980 | PMOSFETS HAVING INDIUM OR GALLIUM DOPED BURIED CHANNELS AND N+ POLYSILICON GATES AND CMOS DEVICES FABRICATED THEREFROM | Nov 30, 1994 | Abandoned |
Array
(
[id] => 3116186
[patent_doc_number] => 05465003
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-11-07
[patent_title] => 'Planarized local oxidation by trench-around technology'
[patent_app_type] => 1
[patent_app_number] => 8/347674
[patent_app_country] => US
[patent_app_date] => 1994-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 2199
[patent_no_of_claims] => 10
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/465/05465003.pdf
[firstpage_image] =>[orig_patent_app_number] => 347674
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/347674 | Planarized local oxidation by trench-around technology | Nov 30, 1994 | Issued |
Array
(
[id] => 3534187
[patent_doc_number] => 05583361
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-10
[patent_title] => 'Semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/347842
[patent_app_country] => US
[patent_app_date] => 1994-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 2385
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/583/05583361.pdf
[firstpage_image] =>[orig_patent_app_number] => 347842
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/347842 | Semiconductor device | Nov 30, 1994 | Issued |
| 08/348950 | MOSFET HAVING IMPROVED DRIVING PERFORMANCE | Nov 24, 1994 | Abandoned |
| 08/345818 | PROCESS FOR PRODUCING A SEMICONDUCTOR DEVICE | Nov 20, 1994 | Abandoned |
| 08/345406 | SEMICONDUCTOR DEVICE WITH TRIPLE WELLS | Nov 20, 1994 | Abandoned |
| 08/341318 | POWER SEMICONDUCTOR DEVICE HAVING IMPROVED REVERSE RECOVERY VOLTAGE | Nov 16, 1994 | Abandoned |
Array
(
[id] => 3530667
[patent_doc_number] => 05541439
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-30
[patent_title] => 'Layout for a high voltage darlington pair'
[patent_app_type] => 1
[patent_app_number] => 8/341250
[patent_app_country] => US
[patent_app_date] => 1994-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 3021
[patent_no_of_claims] => 34
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/541/05541439.pdf
[firstpage_image] =>[orig_patent_app_number] => 341250
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/341250 | Layout for a high voltage darlington pair | Nov 16, 1994 | Issued |
