
Steven J. Fulk
Examiner (ID: 8597)
| Most Active Art Unit | 2891 |
| Art Unit(s) | 2891, OPLA, PTAB |
| Total Applications | 629 |
| Issued Applications | 486 |
| Pending Applications | 6 |
| Abandoned Applications | 137 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5236600
[patent_doc_number] => 20070128757
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-06-07
[patent_title] => 'Method for forming comb electrodes using self-alignment etching'
[patent_app_type] => utility
[patent_app_number] => 11/588298
[patent_app_country] => US
[patent_app_date] => 2006-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 2812
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0128/20070128757.pdf
[firstpage_image] =>[orig_patent_app_number] => 11588298
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/588298 | Method for forming comb electrodes using self-alignment etching | Oct 26, 2006 | Abandoned |
Array
(
[id] => 4955031
[patent_doc_number] => 20080188055
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-08-07
[patent_title] => 'Metal-insulator-metal structure and method of forming the same'
[patent_app_type] => utility
[patent_app_number] => 11/586528
[patent_app_country] => US
[patent_app_date] => 2006-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2732
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0188/20080188055.pdf
[firstpage_image] =>[orig_patent_app_number] => 11586528
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/586528 | Method of forming metal-insulator-metal structure | Oct 25, 2006 | Issued |
Array
(
[id] => 4952655
[patent_doc_number] => 20080185679
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-08-07
[patent_title] => 'INDUCTOR LAYOUT AND MANUFACTURING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 11/550809
[patent_app_country] => US
[patent_app_date] => 2006-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3190
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0185/20080185679.pdf
[firstpage_image] =>[orig_patent_app_number] => 11550809
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/550809 | INDUCTOR LAYOUT AND MANUFACTURING METHOD THEREOF | Oct 18, 2006 | Abandoned |
Array
(
[id] => 7530740
[patent_doc_number] => 07842963
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-11-30
[patent_title] => 'Electrical contacts for a semiconductor light emitting apparatus'
[patent_app_type] => utility
[patent_app_number] => 11/550488
[patent_app_country] => US
[patent_app_date] => 2006-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 14
[patent_no_of_words] => 5416
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 191
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/842/07842963.pdf
[firstpage_image] =>[orig_patent_app_number] => 11550488
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/550488 | Electrical contacts for a semiconductor light emitting apparatus | Oct 17, 2006 | Issued |
Array
(
[id] => 5051508
[patent_doc_number] => 20070032053
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-02-08
[patent_title] => 'Method of producing silicon carbide semiconductor substrate, silicon carbide semiconductor substrate obtained thereby and silicon carbide semiconductor using the same'
[patent_app_type] => utility
[patent_app_number] => 11/580978
[patent_app_country] => US
[patent_app_date] => 2006-10-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4152
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0032/20070032053.pdf
[firstpage_image] =>[orig_patent_app_number] => 11580978
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/580978 | Method of producing silicon carbide semiconductor substrate, silicon carbide semiconductor substrate obtained thereby and silicon carbide semiconductor using the same | Oct 15, 2006 | Issued |
Array
(
[id] => 5075362
[patent_doc_number] => 20070015337
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-01-18
[patent_title] => 'Semiconductor device and method for fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 11/527460
[patent_app_country] => US
[patent_app_date] => 2006-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5267
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0015/20070015337.pdf
[firstpage_image] =>[orig_patent_app_number] => 11527460
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/527460 | Semiconductor device and method for fabricating the same | Sep 26, 2006 | Abandoned |
Array
(
[id] => 5168891
[patent_doc_number] => 20070069322
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-03-29
[patent_title] => 'CMOS image sensor and method for manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 11/528178
[patent_app_country] => US
[patent_app_date] => 2006-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4100
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0069/20070069322.pdf
[firstpage_image] =>[orig_patent_app_number] => 11528178
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/528178 | Method for manufacturing a CMOS image sensor | Sep 25, 2006 | Issued |
Array
(
[id] => 5240041
[patent_doc_number] => 20070018532
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-01-25
[patent_title] => 'METHOD FOR MAKING DEVICES USING INK JET PRINTING'
[patent_app_type] => utility
[patent_app_number] => 11/534531
[patent_app_country] => US
[patent_app_date] => 2006-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 5066
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0018/20070018532.pdf
[firstpage_image] =>[orig_patent_app_number] => 11534531
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/534531 | METHOD FOR MAKING DEVICES USING INK JET PRINTING | Sep 21, 2006 | Abandoned |
Array
(
[id] => 572957
[patent_doc_number] => 07459323
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-12-02
[patent_title] => 'Method of manufacturing a thin film transistor array panel'
[patent_app_type] => utility
[patent_app_number] => 11/512805
[patent_app_country] => US
[patent_app_date] => 2006-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 19
[patent_no_of_words] => 5780
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 178
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/459/07459323.pdf
[firstpage_image] =>[orig_patent_app_number] => 11512805
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/512805 | Method of manufacturing a thin film transistor array panel | Aug 29, 2006 | Issued |
Array
(
[id] => 5685962
[patent_doc_number] => 20060284277
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-12-21
[patent_title] => 'Semiconductor device including bit line formed using damascene technique and method of fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 11/510349
[patent_app_country] => US
[patent_app_date] => 2006-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5136
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0284/20060284277.pdf
[firstpage_image] =>[orig_patent_app_number] => 11510349
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/510349 | Semiconductor device including bit line formed using damascene technique and method of fabricating the same | Aug 24, 2006 | Abandoned |
Array
(
[id] => 5884285
[patent_doc_number] => 20060273460
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-12-07
[patent_title] => 'Method and structure for determining thermal cycle reliability'
[patent_app_type] => utility
[patent_app_number] => 11/502196
[patent_app_country] => US
[patent_app_date] => 2006-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4568
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0273/20060273460.pdf
[firstpage_image] =>[orig_patent_app_number] => 11502196
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/502196 | Structure for determining thermal cycle reliability | Aug 9, 2006 | Issued |
Array
(
[id] => 168183
[patent_doc_number] => 07666742
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-02-23
[patent_title] => 'Method of fabricating semiconductor devices having a recessed active edge'
[patent_app_type] => utility
[patent_app_number] => 11/462949
[patent_app_country] => US
[patent_app_date] => 2006-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 8578
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/666/07666742.pdf
[firstpage_image] =>[orig_patent_app_number] => 11462949
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/462949 | Method of fabricating semiconductor devices having a recessed active edge | Aug 6, 2006 | Issued |
Array
(
[id] => 102033
[patent_doc_number] => 07727841
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-06-01
[patent_title] => 'Method of manufacturing semiconductor device with dual gates'
[patent_app_type] => utility
[patent_app_number] => 11/497998
[patent_app_country] => US
[patent_app_date] => 2006-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 8677
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 212
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/727/07727841.pdf
[firstpage_image] =>[orig_patent_app_number] => 11497998
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/497998 | Method of manufacturing semiconductor device with dual gates | Jul 31, 2006 | Issued |
Array
(
[id] => 151681
[patent_doc_number] => 07678655
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-03-16
[patent_title] => 'Spacer layer etch method providing enhanced microelectronic device performance'
[patent_app_type] => utility
[patent_app_number] => 11/495348
[patent_app_country] => US
[patent_app_date] => 2006-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 2274
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/678/07678655.pdf
[firstpage_image] =>[orig_patent_app_number] => 11495348
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/495348 | Spacer layer etch method providing enhanced microelectronic device performance | Jul 27, 2006 | Issued |
Array
(
[id] => 5239739
[patent_doc_number] => 20070018230
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-01-25
[patent_title] => 'Eeprom and methods of fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 11/490768
[patent_app_country] => US
[patent_app_date] => 2006-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4669
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0018/20070018230.pdf
[firstpage_image] =>[orig_patent_app_number] => 11490768
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/490768 | Eeprom and methods of fabricating the same | Jul 20, 2006 | Abandoned |
Array
(
[id] => 5732954
[patent_doc_number] => 20060258071
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-16
[patent_title] => 'Methods of forming field effect transistors'
[patent_app_type] => utility
[patent_app_number] => 11/490681
[patent_app_country] => US
[patent_app_date] => 2006-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4361
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0258/20060258071.pdf
[firstpage_image] =>[orig_patent_app_number] => 11490681
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/490681 | Methods of forming field effect transistors | Jul 20, 2006 | Issued |
Array
(
[id] => 4465822
[patent_doc_number] => 07936031
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-05-03
[patent_title] => 'MEMS devices having support structures'
[patent_app_type] => utility
[patent_app_number] => 11/491490
[patent_app_country] => US
[patent_app_date] => 2006-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 38
[patent_figures_cnt] => 101
[patent_no_of_words] => 20691
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/936/07936031.pdf
[firstpage_image] =>[orig_patent_app_number] => 11491490
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/491490 | MEMS devices having support structures | Jul 20, 2006 | Issued |
Array
(
[id] => 159182
[patent_doc_number] => 07674675
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-03-09
[patent_title] => 'Method of forming an integrated SOI fingered decoupling capacitor'
[patent_app_type] => utility
[patent_app_number] => 11/485599
[patent_app_country] => US
[patent_app_date] => 2006-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 3916
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/674/07674675.pdf
[firstpage_image] =>[orig_patent_app_number] => 11485599
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/485599 | Method of forming an integrated SOI fingered decoupling capacitor | Jul 11, 2006 | Issued |
Array
(
[id] => 4551207
[patent_doc_number] => 07820470
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-10-26
[patent_title] => 'Manufacturing method of micro-electro-mechanical device'
[patent_app_type] => utility
[patent_app_number] => 11/456729
[patent_app_country] => US
[patent_app_date] => 2006-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 50
[patent_no_of_words] => 15411
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/820/07820470.pdf
[firstpage_image] =>[orig_patent_app_number] => 11456729
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/456729 | Manufacturing method of micro-electro-mechanical device | Jul 10, 2006 | Issued |
Array
(
[id] => 5659176
[patent_doc_number] => 20060249772
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-09
[patent_title] => 'Memory circuitry'
[patent_app_type] => utility
[patent_app_number] => 11/481660
[patent_app_country] => US
[patent_app_date] => 2006-07-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2662
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0249/20060249772.pdf
[firstpage_image] =>[orig_patent_app_number] => 11481660
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/481660 | Memory circuitry | Jul 4, 2006 | Issued |