
Steven J. Fulk
Examiner (ID: 8597)
| Most Active Art Unit | 2891 |
| Art Unit(s) | 2891, OPLA, PTAB |
| Total Applications | 629 |
| Issued Applications | 486 |
| Pending Applications | 6 |
| Abandoned Applications | 137 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7140226
[patent_doc_number] => 20050116352
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-02
[patent_title] => 'Acoustic wave device and method of fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 10/986448
[patent_app_country] => US
[patent_app_date] => 2004-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 7776
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 11
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0116/20050116352.pdf
[firstpage_image] =>[orig_patent_app_number] => 10986448
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/986448 | Acoustic wave device and method of fabricating the same | Nov 11, 2004 | Abandoned |
Array
(
[id] => 478391
[patent_doc_number] => 07223647
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-05-29
[patent_title] => 'Method for forming integrated advanced semiconductor device using sacrificial stress layer'
[patent_app_type] => utility
[patent_app_number] => 10/981925
[patent_app_country] => US
[patent_app_date] => 2004-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4382
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/223/07223647.pdf
[firstpage_image] =>[orig_patent_app_number] => 10981925
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/981925 | Method for forming integrated advanced semiconductor device using sacrificial stress layer | Nov 4, 2004 | Issued |
Array
(
[id] => 5863208
[patent_doc_number] => 20060097338
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-05-11
[patent_title] => 'Temperature-compensated resistor and fabrication method therefor'
[patent_app_type] => utility
[patent_app_number] => 10/982009
[patent_app_country] => US
[patent_app_date] => 2004-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3403
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0097/20060097338.pdf
[firstpage_image] =>[orig_patent_app_number] => 10982009
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/982009 | Temperature-compensated resistor and fabrication method therefor | Nov 4, 2004 | Issued |
Array
(
[id] => 7162052
[patent_doc_number] => 20050199931
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-15
[patent_title] => 'Devices and methods for detecting current leakage between deep trench capacitors in dram devices'
[patent_app_type] => utility
[patent_app_number] => 10/979609
[patent_app_country] => US
[patent_app_date] => 2004-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2463
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0199/20050199931.pdf
[firstpage_image] =>[orig_patent_app_number] => 10979609
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/979609 | Devices for detecting current leakage between deep trench capacitors in DRAM devices | Nov 1, 2004 | Issued |
Array
(
[id] => 5805111
[patent_doc_number] => 20060091463
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-05-04
[patent_title] => 'FinFET body contact structure'
[patent_app_type] => utility
[patent_app_number] => 10/977768
[patent_app_country] => US
[patent_app_date] => 2004-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 6109
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0091/20060091463.pdf
[firstpage_image] =>[orig_patent_app_number] => 10977768
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/977768 | FinFET body contact structure | Oct 28, 2004 | Issued |
Array
(
[id] => 5807813
[patent_doc_number] => 20060094168
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-05-04
[patent_title] => 'Method of forming a thin film component'
[patent_app_type] => utility
[patent_app_number] => 10/977068
[patent_app_country] => US
[patent_app_date] => 2004-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 6260
[patent_no_of_claims] => 64
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0094/20060094168.pdf
[firstpage_image] =>[orig_patent_app_number] => 10977068
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/977068 | Method of forming a thin film component | Oct 28, 2004 | Issued |
Array
(
[id] => 475125
[patent_doc_number] => 07226833
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-06-05
[patent_title] => 'Semiconductor device structure and method therefor'
[patent_app_type] => utility
[patent_app_number] => 10/977423
[patent_app_country] => US
[patent_app_date] => 2004-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 2406
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 196
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/226/07226833.pdf
[firstpage_image] =>[orig_patent_app_number] => 10977423
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/977423 | Semiconductor device structure and method therefor | Oct 28, 2004 | Issued |
Array
(
[id] => 5807789
[patent_doc_number] => 20060094143
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-05-04
[patent_title] => 'Micro-displays and their manufacture'
[patent_app_type] => utility
[patent_app_number] => 10/977278
[patent_app_country] => US
[patent_app_date] => 2004-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 2611
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0094/20060094143.pdf
[firstpage_image] =>[orig_patent_app_number] => 10977278
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/977278 | Micro-displays and their manufacture | Oct 28, 2004 | Issued |
Array
(
[id] => 7144166
[patent_doc_number] => 20050118742
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-02
[patent_title] => 'Method for reducing the adhesive properties of MEMS and anti-adhesion-coated device'
[patent_app_type] => utility
[patent_app_number] => 10/978018
[patent_app_country] => US
[patent_app_date] => 2004-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4184
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0118/20050118742.pdf
[firstpage_image] =>[orig_patent_app_number] => 10978018
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/978018 | Method for reducing the adhesive properties of MEMS and anti-adhesion-coated device | Oct 27, 2004 | Abandoned |
Array
(
[id] => 5743237
[patent_doc_number] => 20060088962
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-04-27
[patent_title] => 'Method of forming a solution processed transistor having a multilayer dielectric'
[patent_app_type] => utility
[patent_app_number] => 10/972229
[patent_app_country] => US
[patent_app_date] => 2004-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5936
[patent_no_of_claims] => 43
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0088/20060088962.pdf
[firstpage_image] =>[orig_patent_app_number] => 10972229
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/972229 | Method of forming a solution processed transistor having a multilayer dielectric | Oct 21, 2004 | Abandoned |
Array
(
[id] => 553077
[patent_doc_number] => 07160769
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-01-09
[patent_title] => 'Channel orientation to enhance transistor performance'
[patent_app_type] => utility
[patent_app_number] => 10/969108
[patent_app_country] => US
[patent_app_date] => 2004-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 1240
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/160/07160769.pdf
[firstpage_image] =>[orig_patent_app_number] => 10969108
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/969108 | Channel orientation to enhance transistor performance | Oct 19, 2004 | Issued |
Array
(
[id] => 612680
[patent_doc_number] => 07148077
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-12-12
[patent_title] => 'Micromechanical structural element having a diaphragm and method for producing such a structural element'
[patent_app_type] => utility
[patent_app_number] => 10/970069
[patent_app_country] => US
[patent_app_date] => 2004-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 26
[patent_no_of_words] => 5632
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/148/07148077.pdf
[firstpage_image] =>[orig_patent_app_number] => 10970069
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/970069 | Micromechanical structural element having a diaphragm and method for producing such a structural element | Oct 18, 2004 | Issued |
Array
(
[id] => 6905670
[patent_doc_number] => 20050101065
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-05-12
[patent_title] => 'Method of manufacturing a semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/956005
[patent_app_country] => US
[patent_app_date] => 2004-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4305
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0101/20050101065.pdf
[firstpage_image] =>[orig_patent_app_number] => 10956005
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/956005 | Method of manufacturing a semiconductor device | Sep 29, 2004 | Abandoned |
Array
(
[id] => 797944
[patent_doc_number] => 07427530
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-09-23
[patent_title] => 'Method of manufacturing photo diodes having a conductive plug contact to a buried layer'
[patent_app_type] => utility
[patent_app_number] => 10/953438
[patent_app_country] => US
[patent_app_date] => 2004-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 4830
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/427/07427530.pdf
[firstpage_image] =>[orig_patent_app_number] => 10953438
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/953438 | Method of manufacturing photo diodes having a conductive plug contact to a buried layer | Sep 28, 2004 | Issued |
Array
(
[id] => 5637545
[patent_doc_number] => 20060068518
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-30
[patent_title] => 'Forming vertically aligned liquid crystal mixtures'
[patent_app_type] => utility
[patent_app_number] => 10/954048
[patent_app_country] => US
[patent_app_date] => 2004-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1478
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0068/20060068518.pdf
[firstpage_image] =>[orig_patent_app_number] => 10954048
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/954048 | Forming vertically aligned liquid crystal mixtures | Sep 28, 2004 | Abandoned |
Array
(
[id] => 5718512
[patent_doc_number] => 20060071285
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-04-06
[patent_title] => 'Inducing strain in the channels of metal gate transistors'
[patent_app_type] => utility
[patent_app_number] => 10/953295
[patent_app_country] => US
[patent_app_date] => 2004-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4856
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0071/20060071285.pdf
[firstpage_image] =>[orig_patent_app_number] => 10953295
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/953295 | Inducing strain in the channels of metal gate transistors | Sep 28, 2004 | Issued |
Array
(
[id] => 5634978
[patent_doc_number] => 20060065951
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-30
[patent_title] => 'Structure and method for bipolar transistor having non-uniform collector-base junction'
[patent_app_type] => utility
[patent_app_number] => 10/953751
[patent_app_country] => US
[patent_app_date] => 2004-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 2992
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0065/20060065951.pdf
[firstpage_image] =>[orig_patent_app_number] => 10953751
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/953751 | Structure and method for bipolar transistor having non-uniform collector-base junction | Sep 28, 2004 | Issued |
Array
(
[id] => 138354
[patent_doc_number] => RE041205
[patent_country] => US
[patent_kind] => E1
[patent_issue_date] => 2010-04-06
[patent_title] => 'Method of fabricating a semiconductor device'
[patent_app_type] => reissue
[patent_app_number] => 10/952576
[patent_app_country] => US
[patent_app_date] => 2004-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 3327
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 271
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/RE/041/RE041205.pdf
[firstpage_image] =>[orig_patent_app_number] => 10952576
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/952576 | Method of fabricating a semiconductor device | Sep 27, 2004 | Issued |
Array
(
[id] => 7010950
[patent_doc_number] => 20050064666
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-24
[patent_title] => 'Flash memory and methods of fabricating flash memory'
[patent_app_type] => utility
[patent_app_number] => 10/950218
[patent_app_country] => US
[patent_app_date] => 2004-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 2318
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0064/20050064666.pdf
[firstpage_image] =>[orig_patent_app_number] => 10950218
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/950218 | Method of fabricating flash memory | Sep 23, 2004 | Issued |
Array
(
[id] => 535606
[patent_doc_number] => 07180132
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-02-20
[patent_title] => 'Enhanced RESURF HVPMOS device with stacked hetero-doping RIM and gradual drift region'
[patent_app_type] => utility
[patent_app_number] => 10/942318
[patent_app_country] => US
[patent_app_date] => 2004-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4227
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 185
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/180/07180132.pdf
[firstpage_image] =>[orig_patent_app_number] => 10942318
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/942318 | Enhanced RESURF HVPMOS device with stacked hetero-doping RIM and gradual drift region | Sep 15, 2004 | Issued |