Search

Steven J. Fulk

Examiner (ID: 8597)

Most Active Art Unit
2891
Art Unit(s)
2891, OPLA, PTAB
Total Applications
629
Issued Applications
486
Pending Applications
6
Abandoned Applications
137

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5727053 [patent_doc_number] => 20060057813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-16 [patent_title] => 'METHOD OF FORMING A POLYSILICON RESISTOR' [patent_app_type] => utility [patent_app_number] => 10/711376 [patent_app_country] => US [patent_app_date] => 2004-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1900 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20060057813.pdf [firstpage_image] =>[orig_patent_app_number] => 10711376 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/711376
METHOD OF FORMING A POLYSILICON RESISTOR Sep 14, 2004 Abandoned
Array ( [id] => 9469598 [patent_doc_number] => 08723231 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-05-13 [patent_title] => 'Semiconductor die micro electro-mechanical switch management system and method' [patent_app_type] => utility [patent_app_number] => 10/942209 [patent_app_country] => US [patent_app_date] => 2004-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5187 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 10942209 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/942209
Semiconductor die micro electro-mechanical switch management system and method Sep 14, 2004 Issued
Array ( [id] => 5724223 [patent_doc_number] => 20060054983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-16 [patent_title] => 'Post-release capacitance enhancement in micromachined devices and a method of performing the same' [patent_app_type] => utility [patent_app_number] => 10/943097 [patent_app_country] => US [patent_app_date] => 2004-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5055 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20060054983.pdf [firstpage_image] =>[orig_patent_app_number] => 10943097 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/943097
Post-release capacitance enhancement in micromachined devices and a method of performing the same Sep 14, 2004 Issued
Array ( [id] => 7178659 [patent_doc_number] => 20050124083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/936738 [patent_app_country] => US [patent_app_date] => 2004-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6603 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20050124083.pdf [firstpage_image] =>[orig_patent_app_number] => 10936738 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/936738
Method for manufacturing semiconductor device Sep 7, 2004 Issued
Array ( [id] => 7253029 [patent_doc_number] => 20050142673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/935974 [patent_app_country] => US [patent_app_date] => 2004-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7180 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20050142673.pdf [firstpage_image] =>[orig_patent_app_number] => 10935974 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/935974
Method for manufacturing semiconductor device Sep 7, 2004 Issued
Array ( [id] => 504434 [patent_doc_number] => 07202100 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-04-10 [patent_title] => 'Method of manufacturing a cloverleaf microgyroscope and cloverleaf microgyroscope' [patent_app_type] => utility [patent_app_number] => 10/933853 [patent_app_country] => US [patent_app_date] => 2004-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 78 [patent_no_of_words] => 8939 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/202/07202100.pdf [firstpage_image] =>[orig_patent_app_number] => 10933853 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/933853
Method of manufacturing a cloverleaf microgyroscope and cloverleaf microgyroscope Sep 2, 2004 Issued
Array ( [id] => 428963 [patent_doc_number] => 07268399 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-11 [patent_title] => 'Enhanced PMOS via transverse stress' [patent_app_type] => utility [patent_app_number] => 10/930638 [patent_app_country] => US [patent_app_date] => 2004-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1756 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/268/07268399.pdf [firstpage_image] =>[orig_patent_app_number] => 10930638 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/930638
Enhanced PMOS via transverse stress Aug 30, 2004 Issued
Array ( [id] => 7253203 [patent_doc_number] => 20050142708 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Method for forming polycrystalline silicon film' [patent_app_type] => utility [patent_app_number] => 10/930011 [patent_app_country] => US [patent_app_date] => 2004-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3014 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20050142708.pdf [firstpage_image] =>[orig_patent_app_number] => 10930011 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/930011
Method for forming polycrystalline silicon film Aug 29, 2004 Abandoned
Array ( [id] => 7140140 [patent_doc_number] => 20050116312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-02 [patent_title] => 'Semiconductor device with trench isolation structure and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 10/927668 [patent_app_country] => US [patent_app_date] => 2004-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5375 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20050116312.pdf [firstpage_image] =>[orig_patent_app_number] => 10927668 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/927668
Method for fabricating semiconductor device with trench isolation structure Aug 26, 2004 Issued
Array ( [id] => 7154237 [patent_doc_number] => 20050082535 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-21 [patent_title] => 'Thin film transistor array panel and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 10/926719 [patent_app_country] => US [patent_app_date] => 2004-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5715 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20050082535.pdf [firstpage_image] =>[orig_patent_app_number] => 10926719 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/926719
Thin film transistor array panel and manufacturing method thereof Aug 25, 2004 Issued
Array ( [id] => 5590985 [patent_doc_number] => 20060040437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-23 [patent_title] => 'Methods of forming field effect transistors' [patent_app_type] => utility [patent_app_number] => 10/925100 [patent_app_country] => US [patent_app_date] => 2004-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4361 [patent_no_of_claims] => 63 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20060040437.pdf [firstpage_image] =>[orig_patent_app_number] => 10925100 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/925100
Methods of forming field effect transistors Aug 22, 2004 Issued
Array ( [id] => 542720 [patent_doc_number] => 07166546 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-23 [patent_title] => 'Planarization for integrated circuits' [patent_app_type] => utility [patent_app_number] => 10/923435 [patent_app_country] => US [patent_app_date] => 2004-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1077 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/166/07166546.pdf [firstpage_image] =>[orig_patent_app_number] => 10923435 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/923435
Planarization for integrated circuits Aug 19, 2004 Issued
Array ( [id] => 5797685 [patent_doc_number] => 20060034006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-16 [patent_title] => 'Hinge for micro-mirror devices' [patent_app_type] => utility [patent_app_number] => 10/918677 [patent_app_country] => US [patent_app_date] => 2004-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3161 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20060034006.pdf [firstpage_image] =>[orig_patent_app_number] => 10918677 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/918677
Hinge for micro-mirror devices Aug 13, 2004 Issued
Array ( [id] => 638285 [patent_doc_number] => 07126182 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-24 [patent_title] => 'Memory circuitry' [patent_app_type] => utility [patent_app_number] => 10/918613 [patent_app_country] => US [patent_app_date] => 2004-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2621 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/126/07126182.pdf [firstpage_image] =>[orig_patent_app_number] => 10918613 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/918613
Memory circuitry Aug 12, 2004 Issued
Array ( [id] => 274197 [patent_doc_number] => 07560361 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-14 [patent_title] => 'Method of forming gate stack for semiconductor electronic device' [patent_app_type] => utility [patent_app_number] => 10/917055 [patent_app_country] => US [patent_app_date] => 2004-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 4501 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/560/07560361.pdf [firstpage_image] =>[orig_patent_app_number] => 10917055 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/917055
Method of forming gate stack for semiconductor electronic device Aug 11, 2004 Issued
Array ( [id] => 6971877 [patent_doc_number] => 20050037587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-17 [patent_title] => 'Heterojunction bipolar transistor' [patent_app_type] => utility [patent_app_number] => 10/914482 [patent_app_country] => US [patent_app_date] => 2004-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4068 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20050037587.pdf [firstpage_image] =>[orig_patent_app_number] => 10914482 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/914482
Heterojunction bipolar transistor Aug 8, 2004 Abandoned
Array ( [id] => 553153 [patent_doc_number] => 07160775 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-09 [patent_title] => 'Method of discharging a semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/912825 [patent_app_country] => US [patent_app_date] => 2004-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 3193 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/160/07160775.pdf [firstpage_image] =>[orig_patent_app_number] => 10912825 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/912825
Method of discharging a semiconductor device Aug 5, 2004 Issued
Array ( [id] => 641736 [patent_doc_number] => 07122435 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-17 [patent_title] => 'Methods, systems and structures for forming improved transistors' [patent_app_type] => utility [patent_app_number] => 10/909515 [patent_app_country] => US [patent_app_date] => 2004-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 27 [patent_no_of_words] => 4907 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/122/07122435.pdf [firstpage_image] =>[orig_patent_app_number] => 10909515 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/909515
Methods, systems and structures for forming improved transistors Aug 1, 2004 Issued
Array ( [id] => 849066 [patent_doc_number] => 07381583 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-06-03 [patent_title] => 'MEMS RF switch integrated process' [patent_app_type] => utility [patent_app_number] => 10/901315 [patent_app_country] => US [patent_app_date] => 2004-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 123 [patent_no_of_words] => 8310 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/381/07381583.pdf [firstpage_image] =>[orig_patent_app_number] => 10901315 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/901315
MEMS RF switch integrated process Jul 26, 2004 Issued
Array ( [id] => 5767956 [patent_doc_number] => 20060019414 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-26 [patent_title] => 'Wiring structure to minimize stress induced void formation' [patent_app_type] => utility [patent_app_number] => 10/899252 [patent_app_country] => US [patent_app_date] => 2004-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11077 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20060019414.pdf [firstpage_image] =>[orig_patent_app_number] => 10899252 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/899252
Wiring structure to minimize stress induced void formation Jul 25, 2004 Issued
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