Search

Steven Sangyul Paik

Supervisory Patent Examiner (ID: 18956, Phone: (571)272-2404 , Office: P/2887 )

Most Active Art Unit
2876
Art Unit(s)
2887, 2876, 2819
Total Applications
603
Issued Applications
400
Pending Applications
85
Abandoned Applications
118

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1433607 [patent_doc_number] => 06340897 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-22 [patent_title] => 'Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory' [patent_app_type] => B1 [patent_app_number] => 09/481781 [patent_app_country] => US [patent_app_date] => 2000-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 13169 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/340/06340897.pdf [firstpage_image] =>[orig_patent_app_number] => 09481781 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/481781
Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory Jan 10, 2000 Issued
Array ( [id] => 1551309 [patent_doc_number] => 06346830 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-12 [patent_title] => 'Data input/output circuit and interface system using the same' [patent_app_type] => B1 [patent_app_number] => 09/478194 [patent_app_country] => US [patent_app_date] => 2000-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3330 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/346/06346830.pdf [firstpage_image] =>[orig_patent_app_number] => 09478194 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/478194
Data input/output circuit and interface system using the same Jan 4, 2000 Issued
Array ( [id] => 4342760 [patent_doc_number] => 06333643 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-25 [patent_title] => 'Hotplug tolerant I/O circuit' [patent_app_type] => 1 [patent_app_number] => 9/476399 [patent_app_country] => US [patent_app_date] => 2000-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3068 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/333/06333643.pdf [firstpage_image] =>[orig_patent_app_number] => 476399 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/476399
Hotplug tolerant I/O circuit Jan 2, 2000 Issued
Array ( [id] => 1492225 [patent_doc_number] => 06417688 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Method and apparatus for implementing a highly robust, fast, and economical five load bus topology based on bit mirroring and a well terminated transmission environment' [patent_app_type] => B1 [patent_app_number] => 09/476585 [patent_app_country] => US [patent_app_date] => 1999-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 6174 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/417/06417688.pdf [firstpage_image] =>[orig_patent_app_number] => 09476585 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/476585
Method and apparatus for implementing a highly robust, fast, and economical five load bus topology based on bit mirroring and a well terminated transmission environment Dec 30, 1999 Issued
Array ( [id] => 4333737 [patent_doc_number] => 06329834 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Reduction of switching noise in integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/475983 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2853 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/329/06329834.pdf [firstpage_image] =>[orig_patent_app_number] => 475983 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/475983
Reduction of switching noise in integrated circuits Dec 29, 1999 Issued
Array ( [id] => 4322141 [patent_doc_number] => 06242950 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Bidirectional data transfer path having increased bandwidth' [patent_app_type] => 1 [patent_app_number] => 9/468191 [patent_app_country] => US [patent_app_date] => 1999-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 5973 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/242/06242950.pdf [firstpage_image] =>[orig_patent_app_number] => 468191 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/468191
Bidirectional data transfer path having increased bandwidth Dec 20, 1999 Issued
Array ( [id] => 1476806 [patent_doc_number] => 06388462 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Waveform shaping digital circuit' [patent_app_type] => B1 [patent_app_number] => 09/446290 [patent_app_country] => US [patent_app_date] => 1999-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 10139 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/388/06388462.pdf [firstpage_image] =>[orig_patent_app_number] => 09446290 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/446290
Waveform shaping digital circuit Dec 20, 1999 Issued
Array ( [id] => 4415817 [patent_doc_number] => 06265897 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Contention based logic gate driving a latch and driven by pulsed clock' [patent_app_type] => 1 [patent_app_number] => 9/466493 [patent_app_country] => US [patent_app_date] => 1999-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 5926 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/265/06265897.pdf [firstpage_image] =>[orig_patent_app_number] => 466493 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/466493
Contention based logic gate driving a latch and driven by pulsed clock Dec 16, 1999 Issued
Array ( [id] => 4353140 [patent_doc_number] => 06285211 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'I/O buffer circuit with pin multiplexing' [patent_app_type] => 1 [patent_app_number] => 9/460535 [patent_app_country] => US [patent_app_date] => 1999-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6926 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/285/06285211.pdf [firstpage_image] =>[orig_patent_app_number] => 460535 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/460535
I/O buffer circuit with pin multiplexing Dec 12, 1999 Issued
Array ( [id] => 6933571 [patent_doc_number] => 20010054915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-27 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => new [patent_app_number] => 09/458999 [patent_app_country] => US [patent_app_date] => 1999-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4143 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20010054915.pdf [firstpage_image] =>[orig_patent_app_number] => 09458999 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/458999
Semiconductor integrated circuit Dec 9, 1999 Abandoned
09/454624 ARCHITECTURES FOR PROGRAMMABLE LOGIC DEVICES Dec 5, 1999 Abandoned
Array ( [id] => 5949030 [patent_doc_number] => 20020005734 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-17 [patent_title] => 'METHOD AND APPARATUS FOR PROGRAMMABLE ACTIVE TERMINATION OF INPUT/OUTPUT DEVICES' [patent_app_type] => new [patent_app_number] => 09/439787 [patent_app_country] => US [patent_app_date] => 1999-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5554 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20020005734.pdf [firstpage_image] =>[orig_patent_app_number] => 09439787 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/439787
Method and apparatus for programmable active termination of input/output devices Nov 11, 1999 Issued
Array ( [id] => 4303326 [patent_doc_number] => 06184708 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Method for selecting slew rate for a programmable device' [patent_app_type] => 1 [patent_app_number] => 9/434415 [patent_app_country] => US [patent_app_date] => 1999-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5286 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/184/06184708.pdf [firstpage_image] =>[orig_patent_app_number] => 434415 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/434415
Method for selecting slew rate for a programmable device Nov 3, 1999 Issued
Array ( [id] => 1495674 [patent_doc_number] => 06342793 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-29 [patent_title] => 'Method and system for sending large numbers of CMOS control signals into a separate quiet analog power domain' [patent_app_type] => B1 [patent_app_number] => 09/433394 [patent_app_country] => US [patent_app_date] => 1999-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5130 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 381 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/342/06342793.pdf [firstpage_image] =>[orig_patent_app_number] => 09433394 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/433394
Method and system for sending large numbers of CMOS control signals into a separate quiet analog power domain Nov 2, 1999 Issued
Array ( [id] => 4415844 [patent_doc_number] => 06229335 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Input/output buffer capable of supporting a multiple of transmission logic buses' [patent_app_type] => 1 [patent_app_number] => 9/417983 [patent_app_country] => US [patent_app_date] => 1999-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3262 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/229/06229335.pdf [firstpage_image] =>[orig_patent_app_number] => 417983 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/417983
Input/output buffer capable of supporting a multiple of transmission logic buses Oct 12, 1999 Issued
Array ( [id] => 1563643 [patent_doc_number] => 06362647 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Programmable function device and memory cell therefor' [patent_app_type] => B1 [patent_app_number] => 09/413693 [patent_app_country] => US [patent_app_date] => 1999-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 8831 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/362/06362647.pdf [firstpage_image] =>[orig_patent_app_number] => 09413693 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/413693
Programmable function device and memory cell therefor Oct 6, 1999 Issued
Array ( [id] => 4312330 [patent_doc_number] => 06252422 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Overvoltage-tolerant interface for intergrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/400953 [patent_app_country] => US [patent_app_date] => 1999-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 34 [patent_no_of_words] => 15758 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/252/06252422.pdf [firstpage_image] =>[orig_patent_app_number] => 400953 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/400953
Overvoltage-tolerant interface for intergrated circuits Sep 21, 1999 Issued
Array ( [id] => 1603403 [patent_doc_number] => 06433585 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Overvoltage-tolerant interface for integrated circuits' [patent_app_type] => B1 [patent_app_number] => 09/401145 [patent_app_country] => US [patent_app_date] => 1999-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 34 [patent_no_of_words] => 16058 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/433/06433585.pdf [firstpage_image] =>[orig_patent_app_number] => 09401145 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/401145
Overvoltage-tolerant interface for integrated circuits Sep 21, 1999 Issued
Array ( [id] => 4390141 [patent_doc_number] => 06278297 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Row decoder with switched power supply' [patent_app_type] => 1 [patent_app_number] => 9/395592 [patent_app_country] => US [patent_app_date] => 1999-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2721 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/278/06278297.pdf [firstpage_image] =>[orig_patent_app_number] => 395592 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/395592
Row decoder with switched power supply Sep 13, 1999 Issued
Array ( [id] => 4368518 [patent_doc_number] => 06255856 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Comparator' [patent_app_type] => 1 [patent_app_number] => 9/382785 [patent_app_country] => US [patent_app_date] => 1999-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2770 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255856.pdf [firstpage_image] =>[orig_patent_app_number] => 382785 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/382785
Comparator Aug 24, 1999 Issued
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