
Steven Sangyul Paik
Supervisory Patent Examiner (ID: 18956, Phone: (571)272-2404 , Office: P/2887 )
| Most Active Art Unit | 2876 |
| Art Unit(s) | 2887, 2876, 2819 |
| Total Applications | 603 |
| Issued Applications | 400 |
| Pending Applications | 85 |
| Abandoned Applications | 118 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1433607
[patent_doc_number] => 06340897
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-01-22
[patent_title] => 'Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory'
[patent_app_type] => B1
[patent_app_number] => 09/481781
[patent_app_country] => US
[patent_app_date] => 2000-01-11
[patent_effective_date] => 0000-00-00
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/340/06340897.pdf
[firstpage_image] =>[orig_patent_app_number] => 09481781
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/481781 | Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory | Jan 10, 2000 | Issued |
Array
(
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[patent_doc_number] => 06346830
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[patent_issue_date] => 2002-02-12
[patent_title] => 'Data input/output circuit and interface system using the same'
[patent_app_type] => B1
[patent_app_number] => 09/478194
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[patent_app_date] => 2000-01-05
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Array
(
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[patent_doc_number] => 06333643
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[patent_kind] => NA
[patent_issue_date] => 2001-12-25
[patent_title] => 'Hotplug tolerant I/O circuit'
[patent_app_type] => 1
[patent_app_number] => 9/476399
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 476399
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/476399 | Hotplug tolerant I/O circuit | Jan 2, 2000 | Issued |
Array
(
[id] => 1492225
[patent_doc_number] => 06417688
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-09
[patent_title] => 'Method and apparatus for implementing a highly robust, fast, and economical five load bus topology based on bit mirroring and a well terminated transmission environment'
[patent_app_type] => B1
[patent_app_number] => 09/476585
[patent_app_country] => US
[patent_app_date] => 1999-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[pdf_file] => patents/06/417/06417688.pdf
[firstpage_image] =>[orig_patent_app_number] => 09476585
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/476585 | Method and apparatus for implementing a highly robust, fast, and economical five load bus topology based on bit mirroring and a well terminated transmission environment | Dec 30, 1999 | Issued |
Array
(
[id] => 4333737
[patent_doc_number] => 06329834
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[patent_issue_date] => 2001-12-11
[patent_title] => 'Reduction of switching noise in integrated circuits'
[patent_app_type] => 1
[patent_app_number] => 9/475983
[patent_app_country] => US
[patent_app_date] => 1999-12-30
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[firstpage_image] =>[orig_patent_app_number] => 475983
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/475983 | Reduction of switching noise in integrated circuits | Dec 29, 1999 | Issued |
Array
(
[id] => 4322141
[patent_doc_number] => 06242950
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[patent_kind] => NA
[patent_issue_date] => 2001-06-05
[patent_title] => 'Bidirectional data transfer path having increased bandwidth'
[patent_app_type] => 1
[patent_app_number] => 9/468191
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[firstpage_image] =>[orig_patent_app_number] => 468191
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/468191 | Bidirectional data transfer path having increased bandwidth | Dec 20, 1999 | Issued |
Array
(
[id] => 1476806
[patent_doc_number] => 06388462
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[patent_title] => 'Waveform shaping digital circuit'
[patent_app_type] => B1
[patent_app_number] => 09/446290
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/446290 | Waveform shaping digital circuit | Dec 20, 1999 | Issued |
Array
(
[id] => 4415817
[patent_doc_number] => 06265897
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[patent_kind] => NA
[patent_issue_date] => 2001-07-24
[patent_title] => 'Contention based logic gate driving a latch and driven by pulsed clock'
[patent_app_type] => 1
[patent_app_number] => 9/466493
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[pdf_file] => patents/06/265/06265897.pdf
[firstpage_image] =>[orig_patent_app_number] => 466493
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/466493 | Contention based logic gate driving a latch and driven by pulsed clock | Dec 16, 1999 | Issued |
Array
(
[id] => 4353140
[patent_doc_number] => 06285211
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[patent_issue_date] => 2001-09-04
[patent_title] => 'I/O buffer circuit with pin multiplexing'
[patent_app_type] => 1
[patent_app_number] => 9/460535
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/460535 | I/O buffer circuit with pin multiplexing | Dec 12, 1999 | Issued |
Array
(
[id] => 6933571
[patent_doc_number] => 20010054915
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[patent_kind] => A1
[patent_issue_date] => 2001-12-27
[patent_title] => 'Semiconductor integrated circuit'
[patent_app_type] => new
[patent_app_number] => 09/458999
[patent_app_country] => US
[patent_app_date] => 1999-12-10
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[pdf_file] => publications/A1/0054/20010054915.pdf
[firstpage_image] =>[orig_patent_app_number] => 09458999
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/458999 | Semiconductor integrated circuit | Dec 9, 1999 | Abandoned |
| 09/454624 | ARCHITECTURES FOR PROGRAMMABLE LOGIC DEVICES | Dec 5, 1999 | Abandoned |
Array
(
[id] => 5949030
[patent_doc_number] => 20020005734
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[patent_issue_date] => 2002-01-17
[patent_title] => 'METHOD AND APPARATUS FOR PROGRAMMABLE ACTIVE TERMINATION OF INPUT/OUTPUT DEVICES'
[patent_app_type] => new
[patent_app_number] => 09/439787
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/439787 | Method and apparatus for programmable active termination of input/output devices | Nov 11, 1999 | Issued |
Array
(
[id] => 4303326
[patent_doc_number] => 06184708
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[patent_issue_date] => 2001-02-06
[patent_title] => 'Method for selecting slew rate for a programmable device'
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Array
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[patent_title] => 'Method and system for sending large numbers of CMOS control signals into a separate quiet analog power domain'
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Array
(
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Array
(
[id] => 1563643
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[patent_title] => 'Programmable function device and memory cell therefor'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/413693 | Programmable function device and memory cell therefor | Oct 6, 1999 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/400953 | Overvoltage-tolerant interface for intergrated circuits | Sep 21, 1999 | Issued |
Array
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Array
(
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Array
(
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[firstpage_image] =>[orig_patent_app_number] => 382785
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/382785 | Comparator | Aug 24, 1999 | Issued |