
Steven T. Sawyer
Examiner (ID: 16766, Phone: (571)270-5469 , Office: P/2847 )
| Most Active Art Unit | 2847 |
| Art Unit(s) | 2835, 2841, 2847 |
| Total Applications | 1157 |
| Issued Applications | 775 |
| Pending Applications | 93 |
| Abandoned Applications | 316 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17566590
[patent_doc_number] => 20220130739
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-28
[patent_title] => FLEXIBLE SUBSTRATE AND SEMICONDUCTOR APPARATUS
[patent_app_type] => utility
[patent_app_number] => 17/450579
[patent_app_country] => US
[patent_app_date] => 2021-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7242
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17450579
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/450579 | Flexible substrate and semiconductor apparatus | Oct 11, 2021 | Issued |
Array
(
[id] => 18287675
[patent_doc_number] => 20230103147
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-30
[patent_title] => LOW STRESS PLANE DESIGN FOR IC PACKAGE SUBSTRATE
[patent_app_type] => utility
[patent_app_number] => 17/490987
[patent_app_country] => US
[patent_app_date] => 2021-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3386
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -23
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17490987
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/490987 | LOW STRESS PLANE DESIGN FOR IC PACKAGE SUBSTRATE | Sep 29, 2021 | Abandoned |
Array
(
[id] => 18632183
[patent_doc_number] => 20230291091
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-09-14
[patent_title] => CIRCUIT BOARD
[patent_app_type] => utility
[patent_app_number] => 18/029005
[patent_app_country] => US
[patent_app_date] => 2021-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6545
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18029005
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/029005 | CIRCUIT BOARD | Sep 27, 2021 | Pending |
Array
(
[id] => 18161935
[patent_doc_number] => 20230028527
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-26
[patent_title] => VIA STRUCTURE, METHOD FOR PREPARING SAME AND METHOD FOR REGULATING IMPEDANCE OF VIA STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 17/486459
[patent_app_country] => US
[patent_app_date] => 2021-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7298
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17486459
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/486459 | VIA STRUCTURE, METHOD FOR PREPARING SAME AND METHOD FOR REGULATING IMPEDANCE OF VIA STRUCTURE | Sep 26, 2021 | Abandoned |
Array
(
[id] => 18026410
[patent_doc_number] => 20220377909
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-24
[patent_title] => ELECTRONIC-COMPONENT CARRIER BOARD AND A WIRING METHOD FOR THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/449032
[patent_app_country] => US
[patent_app_date] => 2021-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1956
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -2
[patent_words_short_claim] => 219
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17449032
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/449032 | Electronic-component carrier board and a wiring method for the same | Sep 26, 2021 | Issued |
Array
(
[id] => 19627468
[patent_doc_number] => 12166324
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-12-10
[patent_title] => Connected structure of substrate and carbon nanotube wire
[patent_app_type] => utility
[patent_app_number] => 17/485172
[patent_app_country] => US
[patent_app_date] => 2021-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 6206
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17485172
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/485172 | Connected structure of substrate and carbon nanotube wire | Sep 23, 2021 | Issued |
Array
(
[id] => 18344221
[patent_doc_number] => 11641713
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-05-02
[patent_title] => Circuit board structure and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 17/483824
[patent_app_country] => US
[patent_app_date] => 2021-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 13
[patent_no_of_words] => 7348
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 253
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17483824
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/483824 | Circuit board structure and manufacturing method thereof | Sep 23, 2021 | Issued |
Array
(
[id] => 17346934
[patent_doc_number] => 20220013265
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-01-13
[patent_title] => ELECTRONIC SUBSTRATES HAVING EMBEDDED DIELECTRIC MAGNETIC MATERIAL TO FORM INDUCTORS
[patent_app_type] => utility
[patent_app_number] => 17/482855
[patent_app_country] => US
[patent_app_date] => 2021-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3930
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 44
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17482855
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/482855 | ELECTRONIC SUBSTRATES HAVING EMBEDDED DIELECTRIC MAGNETIC MATERIAL TO FORM INDUCTORS | Sep 22, 2021 | Abandoned |
Array
(
[id] => 18238066
[patent_doc_number] => 20230070377
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-09
[patent_title] => INTEGRATED STRUCTURE OF CIRCUIT MOLD UNIT OF LTCC ELECTRONIC DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/471053
[patent_app_country] => US
[patent_app_date] => 2021-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2179
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17471053
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/471053 | INTEGRATED STRUCTURE OF CIRCUIT MOLD UNIT OF LTCC ELECTRONIC DEVICE | Sep 8, 2021 | Abandoned |
Array
(
[id] => 18759598
[patent_doc_number] => 20230363087
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-09
[patent_title] => PRINTED CIRCUIT BOARD ASSEMBLY AND ELECTRONIC DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/246036
[patent_app_country] => US
[patent_app_date] => 2021-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12211
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18246036
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/246036 | Printed circuit board assembly and electronic device | Sep 6, 2021 | Issued |
Array
(
[id] => 17304981
[patent_doc_number] => 20210400820
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-23
[patent_title] => PREPARATION OF SOLDER BUMP FOR COMPATIBILITY WITH PRINTED ELECTRONICS AND ENHANCED VIA RELIABILITY
[patent_app_type] => utility
[patent_app_number] => 17/465292
[patent_app_country] => US
[patent_app_date] => 2021-09-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4860
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17465292
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/465292 | PREPARATION OF SOLDER BUMP FOR COMPATIBILITY WITH PRINTED ELECTRONICS AND ENHANCED VIA RELIABILITY | Sep 1, 2021 | Abandoned |
Array
(
[id] => 18641179
[patent_doc_number] => 11765822
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2023-09-19
[patent_title] => Printed circuit boards with meshed conductive structures
[patent_app_type] => utility
[patent_app_number] => 17/463598
[patent_app_country] => US
[patent_app_date] => 2021-09-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 12
[patent_no_of_words] => 2792
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17463598
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/463598 | Printed circuit boards with meshed conductive structures | Aug 31, 2021 | Issued |
Array
(
[id] => 17995287
[patent_doc_number] => 20220361324
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-10
[patent_title] => PRINTED CIRCUIT BOARD
[patent_app_type] => utility
[patent_app_number] => 17/459212
[patent_app_country] => US
[patent_app_date] => 2021-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8353
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17459212
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/459212 | Printed circuit board | Aug 26, 2021 | Issued |
Array
(
[id] => 19062991
[patent_doc_number] => 11942238
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-03-26
[patent_title] => Insulator for stringing block
[patent_app_type] => utility
[patent_app_number] => 17/402975
[patent_app_country] => US
[patent_app_date] => 2021-08-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 2401
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 199
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17402975
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/402975 | Insulator for stringing block | Aug 15, 2021 | Issued |
Array
(
[id] => 18194049
[patent_doc_number] => 20230047568
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-02-16
[patent_title] => PRINTED CIRCUIT BOARDS WITH EMBOSSED METALIZED CIRCUIT TRACES
[patent_app_type] => utility
[patent_app_number] => 17/398491
[patent_app_country] => US
[patent_app_date] => 2021-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6161
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 42
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17398491
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/398491 | PRINTED CIRCUIT BOARDS WITH EMBOSSED METALIZED CIRCUIT TRACES | Aug 9, 2021 | Abandoned |
Array
(
[id] => 17234220
[patent_doc_number] => 20210360777
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-11-18
[patent_title] => METHOD FOR MANUFACTURING CERAMIC SUBSTRATE AND CERAMIC SUBSTRATE
[patent_app_type] => utility
[patent_app_number] => 17/391770
[patent_app_country] => US
[patent_app_date] => 2021-08-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4746
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17391770
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/391770 | Method for manufacturing ceramic substrate and ceramic substrate | Aug 1, 2021 | Issued |
Array
(
[id] => 18723266
[patent_doc_number] => 11800644
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-10-24
[patent_title] => Power electronic switching device, power semiconductor module therewith and method for production
[patent_app_type] => utility
[patent_app_number] => 17/385320
[patent_app_country] => US
[patent_app_date] => 2021-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 3839
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17385320
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/385320 | Power electronic switching device, power semiconductor module therewith and method for production | Jul 25, 2021 | Issued |
Array
(
[id] => 18586459
[patent_doc_number] => 20230268724
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-08-24
[patent_title] => ELECTRICAL CONDUIT JUNCTION BOXES
[patent_app_type] => utility
[patent_app_number] => 18/005466
[patent_app_country] => US
[patent_app_date] => 2021-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7588
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18005466
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/005466 | ELECTRICAL CONDUIT JUNCTION BOXES | Jul 12, 2021 | Pending |
Array
(
[id] => 17190778
[patent_doc_number] => 20210337663
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-10-28
[patent_title] => MULTILAYER WIRING SUBSTRATE
[patent_app_type] => utility
[patent_app_number] => 17/368905
[patent_app_country] => US
[patent_app_date] => 2021-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7760
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17368905
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/368905 | Multilayer wiring substrate | Jul 6, 2021 | Issued |
Array
(
[id] => 17147086
[patent_doc_number] => 20210315100
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-10-07
[patent_title] => LAYERED BODY AND ELECTRONIC COMPONENT
[patent_app_type] => utility
[patent_app_number] => 17/351633
[patent_app_country] => US
[patent_app_date] => 2021-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5449
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17351633
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/351633 | Layered body and electronic component | Jun 17, 2021 | Issued |