Search

Stuart L. Hendrickson

Examiner (ID: 3648, Phone: (571)272-1351 , Office: P/1736 )

Most Active Art Unit
1736
Art Unit(s)
1206, 1793, 1754, 1103, 1736
Total Applications
2465
Issued Applications
1555
Pending Applications
254
Abandoned Applications
686

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20296497 [patent_doc_number] => 20250321740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-16 [patent_title] => Segment Load and Stores [patent_app_type] => utility [patent_app_number] => 19/017172 [patent_app_country] => US [patent_app_date] => 2025-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3394 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19017172 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/017172
Segment Load and Stores Jan 9, 2025 Pending
Array ( [id] => 20738274 [patent_doc_number] => 20260147575 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-05-28 [patent_title] => BRANCH PREDICTION USING MULTIPLE TABLES [patent_app_type] => utility [patent_app_number] => 18/958603 [patent_app_country] => US [patent_app_date] => 2024-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10524 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18958603 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/958603
BRANCH PREDICTION USING MULTIPLE TABLES Nov 24, 2024 Pending
Array ( [id] => 20380427 [patent_doc_number] => 20250362920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-27 [patent_title] => PROCESSING APPARATUS, METHOD FOR PROCESSING INSTRUCTIONS, AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/938844 [patent_app_country] => US [patent_app_date] => 2024-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2433 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18938844 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/938844
PROCESSING APPARATUS, METHOD FOR PROCESSING INSTRUCTIONS, AND ELECTRONIC DEVICE Nov 5, 2024 Pending
Array ( [id] => 20680362 [patent_doc_number] => 20260119181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-30 [patent_title] => PIPELINE STAGE ALLOCATION [patent_app_type] => utility [patent_app_number] => 18/932968 [patent_app_country] => US [patent_app_date] => 2024-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4831 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18932968 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/932968
PIPELINE STAGE ALLOCATION Oct 30, 2024 Pending
Array ( [id] => 20680363 [patent_doc_number] => 20260119182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-30 [patent_title] => System and Method for Single Instruction, Multiple Data (SIMD) Enhancements of ARM64 Processors [patent_app_type] => utility [patent_app_number] => 18/930526 [patent_app_country] => US [patent_app_date] => 2024-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1100 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18930526 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/930526
System and Method for Single Instruction, Multiple Data (SIMD) Enhancements of ARM64 Processors Oct 28, 2024 Pending
Array ( [id] => 20000604 [patent_doc_number] => 20250138826 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => Processor, Instruction Fetching Method, and Computer System [patent_app_type] => utility [patent_app_number] => 18/919793 [patent_app_country] => US [patent_app_date] => 2024-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18919793 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/919793
Processor, Instruction Fetching Method, and Computer System Oct 17, 2024 Pending
Array ( [id] => 20061585 [patent_doc_number] => 20250199807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => SEMICONDUCTOR DEVICE, DEBUGGING SYSTEM, CONTROL METHOD FOR SEMICONDUCTOR DEVICE, AND DEBUGGING METHOD [patent_app_type] => utility [patent_app_number] => 18/918198 [patent_app_country] => US [patent_app_date] => 2024-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2057 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18918198 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/918198
SEMICONDUCTOR DEVICE, DEBUGGING SYSTEM, CONTROL METHOD FOR SEMICONDUCTOR DEVICE, AND DEBUGGING METHOD Oct 16, 2024 Pending
Array ( [id] => 20629209 [patent_doc_number] => 20260093495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-02 [patent_title] => REGISTER ALLOCATION DECISION [patent_app_type] => utility [patent_app_number] => 18/903258 [patent_app_country] => US [patent_app_date] => 2024-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7540 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18903258 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/903258
REGISTER ALLOCATION DECISION Sep 30, 2024 Pending
Array ( [id] => 19694923 [patent_doc_number] => 20250013468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => INSTRUCTION TRANSLATION METHOD AND RELATED DEVICE THEREOF [patent_app_type] => utility [patent_app_number] => 18/898309 [patent_app_country] => US [patent_app_date] => 2024-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11832 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18898309 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/898309
Instruction translation method and related device thereof Sep 25, 2024 Issued
Array ( [id] => 20616711 [patent_doc_number] => 20260086807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-26 [patent_title] => Method for improving GPU efficiency via programmatic tests of synchronization primitive progress [patent_app_type] => utility [patent_app_number] => 18/898080 [patent_app_country] => US [patent_app_date] => 2024-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4370 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18898080 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/898080
Method for improving GPU efficiency via programmatic tests of synchronization primitive progress Sep 25, 2024 Pending
Array ( [id] => 20601705 [patent_doc_number] => 20260079714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-19 [patent_title] => DATA PROCESSING ARRAY [patent_app_type] => utility [patent_app_number] => 18/889939 [patent_app_country] => US [patent_app_date] => 2024-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6645 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18889939 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/889939
DATA PROCESSING ARRAY Sep 18, 2024 Pending
Array ( [id] => 19878477 [patent_doc_number] => 20250110734 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => Operand Selection Circuitry [patent_app_type] => utility [patent_app_number] => 18/818134 [patent_app_country] => US [patent_app_date] => 2024-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11563 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18818134 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/818134
Operand Selection Circuitry Aug 27, 2024 Pending
Array ( [id] => 19787284 [patent_doc_number] => 20250060963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => SYSTEMS, APPARATUSES, AND METHODS FOR CHAINED FUSED MULTIPLY ADD [patent_app_type] => utility [patent_app_number] => 18/815382 [patent_app_country] => US [patent_app_date] => 2024-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21760 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18815382 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/815382
SYSTEMS, APPARATUSES, AND METHODS FOR CHAINED FUSED MULTIPLY ADD Aug 25, 2024 Pending
Array ( [id] => 20181266 [patent_doc_number] => 20250265224 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => DYNAMIC RECONFIGURATION OF A UNIFIED CORE PROCESSOR TO A MULTI-CORE PROCESSOR [patent_app_type] => utility [patent_app_number] => 18/813666 [patent_app_country] => US [patent_app_date] => 2024-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11311 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18813666 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/813666
DYNAMIC RECONFIGURATION OF A UNIFIED CORE PROCESSOR TO A MULTI-CORE PROCESSOR Aug 22, 2024 Pending
Array ( [id] => 20052173 [patent_doc_number] => 20250190395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-12 [patent_title] => DYNAMIC PROCESSOR ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 18/813501 [patent_app_country] => US [patent_app_date] => 2024-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10363 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18813501 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/813501
DYNAMIC PROCESSOR ARCHITECTURE Aug 22, 2024 Pending
Array ( [id] => 20440291 [patent_doc_number] => 12511127 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-30 [patent_title] => Dynamic reconfiguration of a multi-core processor to a unified core [patent_app_type] => utility [patent_app_number] => 18/813657 [patent_app_country] => US [patent_app_date] => 2024-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 11311 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18813657 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/813657
Dynamic reconfiguration of a multi-core processor to a unified core Aug 22, 2024 Issued
Array ( [id] => 20673190 [patent_doc_number] => 12613702 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-28 [patent_title] => Processor and compiler for secure multiparty computation [patent_app_type] => utility [patent_app_number] => 18/811392 [patent_app_country] => US [patent_app_date] => 2024-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3675 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18811392 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/811392
Processor and compiler for secure multiparty computation Aug 20, 2024 Issued
Array ( [id] => 20513377 [patent_doc_number] => 20260037478 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-05 [patent_title] => SYSTEMS AND METHODS FOR PERFORMING DIRECT MEMORY ACCESS DATA TRANSFERS [patent_app_type] => utility [patent_app_number] => 18/790015 [patent_app_country] => US [patent_app_date] => 2024-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 50705 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18790015 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/790015
SYSTEMS AND METHODS FOR PERFORMING DIRECT MEMORY ACCESS DATA TRANSFERS Jul 30, 2024 Pending
Array ( [id] => 19588372 [patent_doc_number] => 20240385929 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => METHOD TO RESET CONFIGURABLE UNITS IN A RECONFIGURABLE PROCESSOR [patent_app_type] => utility [patent_app_number] => 18/788391 [patent_app_country] => US [patent_app_date] => 2024-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17541 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18788391 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/788391
METHOD TO RESET CONFIGURABLE UNITS IN A RECONFIGURABLE PROCESSOR Jul 29, 2024 Pending
Array ( [id] => 20500566 [patent_doc_number] => 20260030026 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-29 [patent_title] => PREDICTIVELY FETCHING A BRANCH BASED ON A FETCH GROUP ADDRESS AND BRANCH HISTORY EARLY IN AN INSTRUCTION FETCH CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/782772 [patent_app_country] => US [patent_app_date] => 2024-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5933 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18782772 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/782772
PREDICTIVELY FETCHING A BRANCH BASED ON A FETCH GROUP ADDRESS AND BRANCH HISTORY EARLY IN AN INSTRUCTION FETCH CIRCUIT Jul 23, 2024 Pending
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