Search

Stuart L. Hendrickson

Examiner (ID: 3648, Phone: (571)272-1351 , Office: P/1736 )

Most Active Art Unit
1736
Art Unit(s)
1206, 1793, 1754, 1103, 1736
Total Applications
2465
Issued Applications
1555
Pending Applications
254
Abandoned Applications
686

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18087262 [patent_doc_number] => 11537395 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-27 [patent_title] => Method for optimizing performance of algorithm using precision scaling [patent_app_type] => utility [patent_app_number] => 17/519079 [patent_app_country] => US [patent_app_date] => 2021-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4306 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17519079 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/519079
Method for optimizing performance of algorithm using precision scaling Nov 3, 2021 Issued
Array ( [id] => 17597809 [patent_doc_number] => 20220147383 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => COOPERATIVE COMPUTING DEVICE AND COOPERATIVE COMPUTING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/517728 [patent_app_country] => US [patent_app_date] => 2021-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4888 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17517728 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/517728
Cooperative computing device and cooperative computing method thereof Nov 2, 2021 Issued
Array ( [id] => 19107774 [patent_doc_number] => 11960884 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Apparatus and method for complex multiplication [patent_app_type] => utility [patent_app_number] => 17/517351 [patent_app_country] => US [patent_app_date] => 2021-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 16662 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 321 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17517351 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/517351
Apparatus and method for complex multiplication Nov 1, 2021 Issued
Array ( [id] => 18154797 [patent_doc_number] => 11567775 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-01-31 [patent_title] => Dynamic generation of logic for computing systems [patent_app_type] => utility [patent_app_number] => 17/510100 [patent_app_country] => US [patent_app_date] => 2021-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 8896 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17510100 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/510100
Dynamic generation of logic for computing systems Oct 24, 2021 Issued
Array ( [id] => 18668402 [patent_doc_number] => 11775302 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Histogram operation [patent_app_type] => utility [patent_app_number] => 17/509218 [patent_app_country] => US [patent_app_date] => 2021-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 40 [patent_no_of_words] => 23474 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17509218 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/509218
Histogram operation Oct 24, 2021 Issued
Array ( [id] => 18262062 [patent_doc_number] => 11609763 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-21 [patent_title] => Performance scaling for binary translation [patent_app_type] => utility [patent_app_number] => 17/510167 [patent_app_country] => US [patent_app_date] => 2021-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4995 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17510167 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/510167
Performance scaling for binary translation Oct 24, 2021 Issued
Array ( [id] => 18400871 [patent_doc_number] => 11663009 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-30 [patent_title] => Supporting large-word operations in a reduced instruction set computer ("RISC") processor [patent_app_type] => utility [patent_app_number] => 17/450987 [patent_app_country] => US [patent_app_date] => 2021-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11044 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17450987 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/450987
Supporting large-word operations in a reduced instruction set computer ("RISC") processor Oct 13, 2021 Issued
Array ( [id] => 18218176 [patent_doc_number] => 11593113 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-28 [patent_title] => Widening memory access to an aligned address for unaligned memory operations [patent_app_type] => utility [patent_app_number] => 17/449940 [patent_app_country] => US [patent_app_date] => 2021-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 9384 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17449940 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/449940
Widening memory access to an aligned address for unaligned memory operations Oct 3, 2021 Issued
Array ( [id] => 17372256 [patent_doc_number] => 20220027308 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => Control Barrier Network for Reconfigurable Data Processors [patent_app_type] => utility [patent_app_number] => 17/492403 [patent_app_country] => US [patent_app_date] => 2021-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7202 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17492403 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/492403
Control barrier network for reconfigurable data processors Sep 30, 2021 Issued
Array ( [id] => 17507403 [patent_doc_number] => 20220100506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => GRAPHICS PROCESOR UNIT WITH OPPORTUNISTIC INTER-PATH RECONVERGENCE [patent_app_type] => utility [patent_app_number] => 17/491057 [patent_app_country] => US [patent_app_date] => 2021-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7367 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17491057 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/491057
Graphics processor unit with opportunistic inter-path reconvergence Sep 29, 2021 Issued
Array ( [id] => 19841929 [patent_doc_number] => 12254320 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Method and system for processing instruction timeout, and device and medium [patent_app_type] => utility [patent_app_number] => 18/039268 [patent_app_country] => US [patent_app_date] => 2021-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 4770 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18039268 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/039268
Method and system for processing instruction timeout, and device and medium Sep 28, 2021 Issued
Array ( [id] => 20331435 [patent_doc_number] => 12461710 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Reformatting matrices to improve computing efficiency [patent_app_type] => utility [patent_app_number] => 17/485455 [patent_app_country] => US [patent_app_date] => 2021-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3573 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17485455 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/485455
Reformatting matrices to improve computing efficiency Sep 25, 2021 Issued
Array ( [id] => 18286040 [patent_doc_number] => 20230101512 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => SHARED PREFETCH INSTRUCTION AND SUPPORT [patent_app_type] => utility [patent_app_number] => 17/485372 [patent_app_country] => US [patent_app_date] => 2021-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14533 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17485372 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/485372
Shared prefetch instruction and support Sep 24, 2021 Issued
Array ( [id] => 19841928 [patent_doc_number] => 12254319 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Scalable toggle point control circuitry for a clustered decode pipeline [patent_app_type] => utility [patent_app_number] => 17/484969 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 16078 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17484969 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/484969
Scalable toggle point control circuitry for a clustered decode pipeline Sep 23, 2021 Issued
Array ( [id] => 17706806 [patent_doc_number] => 20220206812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => METHOD AND SYSTEM FOR CONVERTING INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 17/471343 [patent_app_country] => US [patent_app_date] => 2021-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20207 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17471343 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/471343
Method and system for converting instructions Sep 9, 2021 Issued
Array ( [id] => 17706807 [patent_doc_number] => 20220206813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => METHOD AND SYSTEM FOR EXECUTING NEW INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 17/471440 [patent_app_country] => US [patent_app_date] => 2021-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20268 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17471440 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/471440
Method and system for executing new instructions Sep 9, 2021 Issued
Array ( [id] => 17794222 [patent_doc_number] => 20220253314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => METHOD PERFORMED BY A MICROCONTROLLER FOR MANAGING A NOP INSTRUCTION AND CORRESPONDING MICROCONTROLLER [patent_app_type] => utility [patent_app_number] => 17/465654 [patent_app_country] => US [patent_app_date] => 2021-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5207 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17465654 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/465654
Method performed by a microcontroller for managing a NOP instruction and corresponding microcontroller Sep 1, 2021 Issued
Array ( [id] => 20145585 [patent_doc_number] => 12379927 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => BFLOAT16 scale and/or reduce instructions [patent_app_type] => utility [patent_app_number] => 17/463382 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 28 [patent_no_of_words] => 10549 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17463382 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/463382
BFLOAT16 scale and/or reduce instructions Aug 30, 2021 Issued
Array ( [id] => 18222582 [patent_doc_number] => 20230061576 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => METHOD AND SYSTEM FOR HARDWARE-ASSISTED PRE-EXECUTION [patent_app_type] => utility [patent_app_number] => 17/412200 [patent_app_country] => US [patent_app_date] => 2021-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8051 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17412200 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/412200
Method and system for hard ware-assisted pre-execution Aug 24, 2021 Issued
Array ( [id] => 18212671 [patent_doc_number] => 20230058935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => MANAGING RETURN PARAMETER ALLOCATION [patent_app_type] => utility [patent_app_number] => 17/405646 [patent_app_country] => US [patent_app_date] => 2021-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20148 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17405646 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/405646
MANAGING RETURN PARAMETER ALLOCATION Aug 17, 2021 Abandoned
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