Search

Stuart L. Hendrickson

Examiner (ID: 3648, Phone: (571)272-1351 , Office: P/1736 )

Most Active Art Unit
1736
Art Unit(s)
1206, 1793, 1754, 1103, 1736
Total Applications
2465
Issued Applications
1555
Pending Applications
254
Abandoned Applications
686

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17260905 [patent_doc_number] => 20210373890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => Conditional Branching Control for a Multi-Threaded, Self-Scheduling Reconfigurable Computing Fabric [patent_app_type] => utility [patent_app_number] => 17/399427 [patent_app_country] => US [patent_app_date] => 2021-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31726 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17399427 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/399427
Conditional branching control for a multi-threaded, self-scheduling reconfigurable computing fabric Aug 10, 2021 Issued
Array ( [id] => 18873552 [patent_doc_number] => 11861366 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Efficient processing of nested loops for computing device with multiple configurable processing elements using multiple spoke counts [patent_app_type] => utility [patent_app_number] => 17/399801 [patent_app_country] => US [patent_app_date] => 2021-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 19331 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17399801 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/399801
Efficient processing of nested loops for computing device with multiple configurable processing elements using multiple spoke counts Aug 10, 2021 Issued
Array ( [id] => 18174209 [patent_doc_number] => 11573921 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-02-07 [patent_title] => Built-in self-test for a programmable vision accelerator of a system on a chip [patent_app_type] => utility [patent_app_number] => 17/391891 [patent_app_country] => US [patent_app_date] => 2021-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 61 [patent_no_of_words] => 58329 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17391891 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/391891
Built-in self-test for a programmable vision accelerator of a system on a chip Aug 1, 2021 Issued
Array ( [id] => 18167465 [patent_doc_number] => 20230034072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => APPARATUS AND METHODS EMPLOYING A SHARED READ PORT REGISTER FILE [patent_app_type] => utility [patent_app_number] => 17/389838 [patent_app_country] => US [patent_app_date] => 2021-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7463 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17389838 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/389838
Apparatus and methods employing a shared read post register file Jul 29, 2021 Issued
Array ( [id] => 17771160 [patent_doc_number] => 11403101 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-08-02 [patent_title] => Introducing noise in threaded execution to mitigate cross-thread monitoring [patent_app_type] => utility [patent_app_number] => 17/444125 [patent_app_country] => US [patent_app_date] => 2021-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11556 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17444125 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/444125
Introducing noise in threaded execution to mitigate cross-thread monitoring Jul 29, 2021 Issued
Array ( [id] => 18104184 [patent_doc_number] => 11544070 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-03 [patent_title] => Efficient mitigation of side-channel based attacks against speculative execution processing architectures [patent_app_type] => utility [patent_app_number] => 17/387240 [patent_app_country] => US [patent_app_date] => 2021-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 11027 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17387240 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/387240
Efficient mitigation of side-channel based attacks against speculative execution processing architectures Jul 27, 2021 Issued
Array ( [id] => 18356676 [patent_doc_number] => 11645076 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-09 [patent_title] => Register pressure target function splitting [patent_app_type] => utility [patent_app_number] => 17/384887 [patent_app_country] => US [patent_app_date] => 2021-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6118 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17384887 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/384887
Register pressure target function splitting Jul 25, 2021 Issued
Array ( [id] => 17230658 [patent_doc_number] => 20210357215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => APPARATUS AND METHOD FOR MULTIPLY, ADD/SUBTRACT, AND ACCUMULATE OF PACKED DATA ELEMENTS [patent_app_type] => utility [patent_app_number] => 17/380930 [patent_app_country] => US [patent_app_date] => 2021-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17201 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17380930 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/380930
APPARATUS AND METHOD FOR MULTIPLY, ADD/SUBTRACT, AND ACCUMULATE OF PACKED DATA ELEMENTS Jul 19, 2021 Abandoned
Array ( [id] => 17423523 [patent_doc_number] => 11256981 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-02-22 [patent_title] => Unbounded parallel implementation of deep neural networks [patent_app_type] => utility [patent_app_number] => 17/373497 [patent_app_country] => US [patent_app_date] => 2021-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 48 [patent_no_of_words] => 24852 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17373497 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/373497
Unbounded parallel implementation of deep neural networks Jul 11, 2021 Issued
Array ( [id] => 18046632 [patent_doc_number] => 11520586 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-06 [patent_title] => Method and apparatus for renaming source operands of instructions [patent_app_type] => utility [patent_app_number] => 17/370098 [patent_app_country] => US [patent_app_date] => 2021-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5151 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17370098 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/370098
Method and apparatus for renaming source operands of instructions Jul 7, 2021 Issued
Array ( [id] => 17358635 [patent_doc_number] => 20220019431 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-20 [patent_title] => INSTRUCTIONS AND LOGIC TO PERFORM FLOATING POINT AND INTEGER OPERATIONS FOR MACHINE LEARNING [patent_app_type] => utility [patent_app_number] => 17/305355 [patent_app_country] => US [patent_app_date] => 2021-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 39344 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17305355 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/305355
Instructions and logic to perform floating point and integer operations for machine learning Jul 5, 2021 Issued
Array ( [id] => 18248062 [patent_doc_number] => 11604649 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-14 [patent_title] => Techniques for efficiently transferring data to a processor [patent_app_type] => utility [patent_app_number] => 17/363561 [patent_app_country] => US [patent_app_date] => 2021-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 18256 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17363561 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/363561
Techniques for efficiently transferring data to a processor Jun 29, 2021 Issued
Array ( [id] => 18095524 [patent_doc_number] => 20220413865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS FOR A HARDWARE ASSISTED HETEROGENEOUS INSTRUCTION SET ARCHITECTURE DISPATCHER [patent_app_type] => utility [patent_app_number] => 17/359306 [patent_app_country] => US [patent_app_date] => 2021-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20529 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17359306 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/359306
Apparatuses, methods, and systems for instructions for a hardware assisted heterogeneous instruction set architecture dispatcher Jun 24, 2021 Issued
Array ( [id] => 19905372 [patent_doc_number] => 12282377 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-22 [patent_title] => Hardware-assisted core frequency and voltage scaling in a poll mode idle loop [patent_app_type] => utility [patent_app_number] => 17/358224 [patent_app_country] => US [patent_app_date] => 2021-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2416 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17358224 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/358224
Hardware-assisted core frequency and voltage scaling in a poll mode idle loop Jun 24, 2021 Issued
Array ( [id] => 18719962 [patent_doc_number] => 11797307 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Range prefetch instruction [patent_app_type] => utility [patent_app_number] => 17/355641 [patent_app_country] => US [patent_app_date] => 2021-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 17537 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17355641 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/355641
Range prefetch instruction Jun 22, 2021 Issued
Array ( [id] => 17454773 [patent_doc_number] => 11269632 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-03-08 [patent_title] => Data conversion to/from selected data type with implied rounding mode [patent_app_type] => utility [patent_app_number] => 17/350418 [patent_app_country] => US [patent_app_date] => 2021-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 36 [patent_no_of_words] => 25338 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17350418 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/350418
Data conversion to/from selected data type with implied rounding mode Jun 16, 2021 Issued
Array ( [id] => 19925290 [patent_doc_number] => 12299576 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Neural network-based inference method and apparatus [patent_app_type] => utility [patent_app_number] => 17/343001 [patent_app_country] => US [patent_app_date] => 2021-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 4546 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17343001 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/343001
Neural network-based inference method and apparatus Jun 8, 2021 Issued
Array ( [id] => 17454774 [patent_doc_number] => 11269633 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-03-08 [patent_title] => System and method for executing a number of NOP instructions after a repeated instruction [patent_app_type] => utility [patent_app_number] => 17/303746 [patent_app_country] => US [patent_app_date] => 2021-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3808 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17303746 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/303746
System and method for executing a number of NOP instructions after a repeated instruction Jun 6, 2021 Issued
Array ( [id] => 17230656 [patent_doc_number] => 20210357213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => HARDWARE APPARATUSES AND METHODS TO SWITCH SHADOW STACK POINTERS [patent_app_type] => utility [patent_app_number] => 17/340632 [patent_app_country] => US [patent_app_date] => 2021-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15399 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17340632 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/340632
Hardware apparatuses and methods to switch shadow stack pointers Jun 6, 2021 Issued
Array ( [id] => 18356677 [patent_doc_number] => 11645077 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-09 [patent_title] => Systems and methods to zero a tile register pair [patent_app_type] => utility [patent_app_number] => 17/335377 [patent_app_country] => US [patent_app_date] => 2021-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 44 [patent_no_of_words] => 24171 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17335377 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/335377
Systems and methods to zero a tile register pair May 31, 2021 Issued
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