Stuart L. Hendrickson

Array ( [id] => 11621752 [patent_doc_number] => 20170131939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-11 [patent_title] => 'TRANSFER DESCRIPTOR FOR MEMORY ACCESS COMMANDS' [patent_app_type] => utility [patent_app_number] => 14/934707 [patent_app_country] => US [patent_app_date] => 2015-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3797 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14934707 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11606492 [patent_doc_number] => 20170123795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-04 [patent_title] => 'TIGHTLY COUPLED PROCESSOR ARRAYS USING COARSE GRAINED RECONFIGURABLE ARCHITECTURE WITH ITERATION LEVEL COMMITS' [patent_app_type] => utility [patent_app_number] => 14/932672 [patent_app_country] => US [patent_app_date] => 2015-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 20508 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14932672 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10695694 [patent_doc_number] => 20160041841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-11 [patent_title] => 'REALIZING JUMPS IN AN EXECUTING PROCESS INSTANCE' [patent_app_type] => utility [patent_app_number] => 14/918553 [patent_app_country] => US [patent_app_date] => 2015-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3527 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14918553 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11523407 [patent_doc_number] => 09606805 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-03-28 [patent_title] => 'Accuracy of operand store compare prediction using confidence counter' [patent_app_type] => utility [patent_app_number] => 14/886465 [patent_app_country] => US [patent_app_date] => 2015-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 9263 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14886465 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11556702 [patent_doc_number] => 20170102948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-13 [patent_title] => 'SYSTEM AND METHOD FOR PREDICTING LATENCY OF A VARIABLE-LATENCY INSTRUCTION' [patent_app_type] => utility [patent_app_number] => 14/879213 [patent_app_country] => US [patent_app_date] => 2015-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5164 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14879213 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10757631 [patent_doc_number] => 20160103784 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-14 [patent_title] => 'ASYMMETRICAL PROCESSOR MEMORY ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 14/878474 [patent_app_country] => US [patent_app_date] => 2015-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3542 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14878474 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11530944 [patent_doc_number] => 20170090922 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-30 [patent_title] => 'Efficient Instruction Pair for Central Processing Unit (CPU) Instruction Design' [patent_app_type] => utility [patent_app_number] => 14/871229 [patent_app_country] => US [patent_app_date] => 2015-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6344 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14871229 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12495219 [patent_doc_number] => 09996358 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-12 [patent_title] => Unified prefetching into instruction cache and branch target buffer [patent_app_type] => utility [patent_app_number] => 14/871417 [patent_app_country] => US [patent_app_date] => 2015-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7149 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14871417 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11530949 [patent_doc_number] => 20170090927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-30 [patent_title] => 'CONTROL TRANSFER INSTRUCTIONS INDICATING INTENT TO CALL OR RETURN' [patent_app_type] => utility [patent_app_number] => 14/870417 [patent_app_country] => US [patent_app_date] => 2015-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4345 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14870417 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16535159 [patent_doc_number] => 10877759 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => Managing the capture of information in applications with prefix instructions [patent_app_type] => utility [patent_app_number] => 14/871979 [patent_app_country] => US [patent_app_date] => 2015-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 10138 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14871979 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13185795 [patent_doc_number] => 10108417 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-23 [patent_title] => Storing narrow produced values for instruction operands directly in a register map in an out-of-order processor [patent_app_type] => utility [patent_app_number] => 14/860032 [patent_app_country] => US [patent_app_date] => 2015-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9814 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14860032 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10739568 [patent_doc_number] => 20160085719 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-24 [patent_title] => 'PRESENTING PIPELINES OF MULTICORE PROCESSORS AS SEPARATE PROCESSOR CORES TO A PROGRAMMING FRAMEWORK' [patent_app_type] => utility [patent_app_number] => 14/858459 [patent_app_country] => US [patent_app_date] => 2015-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3697 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14858459 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12474843 [patent_doc_number] => 09990199 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-05 [patent_title] => Conditional flow with hardware acceleration [patent_app_type] => utility [patent_app_number] => 14/859041 [patent_app_country] => US [patent_app_date] => 2015-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10963 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14859041 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11384837 [patent_doc_number] => 20170010893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-12 [patent_title] => 'BIT-MASKED VARIABLE-PRECISION BARREL SHIFTER' [patent_app_type] => utility [patent_app_number] => 14/856538 [patent_app_country] => US [patent_app_date] => 2015-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10039 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14856538 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10982572 [patent_doc_number] => 20160179516 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'INFORMATION PROCESSING DEVICE AND CONTROL METHOD' [patent_app_type] => utility [patent_app_number] => 14/854076 [patent_app_country] => US [patent_app_date] => 2015-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4450 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14854076 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10493718 [patent_doc_number] => 20150378740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'SELECTIVELY PERFORMING A SINGLE CYCLE WRITE OPERATION WITH ECC IN A DATA PROCESSING SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/852200 [patent_app_country] => US [patent_app_date] => 2015-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13861 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14852200 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10493755 [patent_doc_number] => 20150378776 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'SCHEDULING IN A MULTICORE ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 14/848334 [patent_app_country] => US [patent_app_date] => 2015-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 47 [patent_no_of_words] => 25957 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14848334 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10485581 [patent_doc_number] => 20150370600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-24 [patent_title] => 'SYSTEM HAVING OPERATION QUEUES CORRESPONDING TO OPERATION EXECUTION TIME' [patent_app_type] => utility [patent_app_number] => 14/839257 [patent_app_country] => US [patent_app_date] => 2015-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4967 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14839257 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10470891 [patent_doc_number] => 20150355908 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-10 [patent_title] => 'ADDRESS EXPANSION AND CONTRACTION IN A MULTITHREADING COMPUTER SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/828768 [patent_app_country] => US [patent_app_date] => 2015-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12977 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14828768 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10454106 [patent_doc_number] => 20150339121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-26 [patent_title] => 'THREAD CONTEXT RESTORATION IN A MULTITHREADING COMPUTER SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/819633 [patent_app_country] => US [patent_app_date] => 2015-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 13323 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14819633 [rel_patent_id] =>[rel_patent_doc_number] =>)