Search

Stuart L. Hendrickson

Examiner (ID: 3648, Phone: (571)272-1351 , Office: P/1736 )

Most Active Art Unit
1736
Art Unit(s)
1206, 1793, 1754, 1103, 1736
Total Applications
2465
Issued Applications
1555
Pending Applications
254
Abandoned Applications
686

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10454105 [patent_doc_number] => 20150339120 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-26 [patent_title] => 'DYNAMIC ENABLEMENT OF MULTITHREADING' [patent_app_type] => utility [patent_app_number] => 14/819521 [patent_app_country] => US [patent_app_date] => 2015-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 13082 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14819521 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/819521
Dynamic enablement of multithreading Aug 5, 2015 Issued
Array ( [id] => 14669141 [patent_doc_number] => 10372472 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-06 [patent_title] => System, method, and computer program product for conditionally preventing use of hardware virtualization [patent_app_type] => utility [patent_app_number] => 14/820296 [patent_app_country] => US [patent_app_date] => 2015-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4886 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14820296 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/820296
System, method, and computer program product for conditionally preventing use of hardware virtualization Aug 5, 2015 Issued
Array ( [id] => 12011529 [patent_doc_number] => 09804847 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-31 [patent_title] => 'Thread context preservation in a multithreading computer system' [patent_app_type] => utility [patent_app_number] => 14/819592 [patent_app_country] => US [patent_app_date] => 2015-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 13132 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14819592 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/819592
Thread context preservation in a multithreading computer system Aug 5, 2015 Issued
Array ( [id] => 11423544 [patent_doc_number] => 20170031687 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-02 [patent_title] => 'REGISTER COMPARISON FOR OPERAND STORE COMPARE (OSC) PREDICTION' [patent_app_type] => utility [patent_app_number] => 14/813796 [patent_app_country] => US [patent_app_date] => 2015-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5303 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14813796 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/813796
Register comparison for operand store compare (OSC) prediction Jul 29, 2015 Issued
Array ( [id] => 16706222 [patent_doc_number] => 10956154 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-23 [patent_title] => Signal processing device and method [patent_app_type] => utility [patent_app_number] => 15/741670 [patent_app_country] => US [patent_app_date] => 2015-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4894 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15741670 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/741670
Signal processing device and method Jul 6, 2015 Issued
Array ( [id] => 14427007 [patent_doc_number] => 10318307 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-11 [patent_title] => Scalarization of vector processing [patent_app_type] => utility [patent_app_number] => 14/741505 [patent_app_country] => US [patent_app_date] => 2015-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4655 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14741505 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/741505
Scalarization of vector processing Jun 16, 2015 Issued
Array ( [id] => 11352351 [patent_doc_number] => 20160371091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'TECHNIQUES FOR IMPROVING ISSUE OF INSTRUCTIONS WITH VARIABLE LATENCIES IN A MICROPROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/742427 [patent_app_country] => US [patent_app_date] => 2015-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6337 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14742427 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/742427
TECHNIQUES FOR IMPROVING ISSUE OF INSTRUCTIONS WITH VARIABLE LATENCIES IN A MICROPROCESSOR Jun 16, 2015 Abandoned
Array ( [id] => 14825199 [patent_doc_number] => 10409607 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-10 [patent_title] => Electronic device and method for data processing using virtual register mode [patent_app_type] => utility [patent_app_number] => 14/739236 [patent_app_country] => US [patent_app_date] => 2015-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4150 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14739236 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/739236
Electronic device and method for data processing using virtual register mode Jun 14, 2015 Issued
Array ( [id] => 11086277 [patent_doc_number] => 20160283243 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-29 [patent_title] => 'BRANCH LOOK-AHEAD INSTRUCTION DISASSEMBLING, ASSEMBLING, AND DELIVERING SYSTEM APPARATUS AND METHOD FOR MICROPROCESSOR SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/735147 [patent_app_country] => US [patent_app_date] => 2015-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 10936 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14735147 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/735147
BRANCH LOOK-AHEAD INSTRUCTION DISASSEMBLING, ASSEMBLING, AND DELIVERING SYSTEM APPARATUS AND METHOD FOR MICROPROCESSOR SYSTEM Jun 9, 2015 Abandoned
Array ( [id] => 11860808 [patent_doc_number] => 09740491 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-22 [patent_title] => 'Instruction group formation techniques for decode-time instruction optimization based on feedback' [patent_app_type] => utility [patent_app_number] => 14/734825 [patent_app_country] => US [patent_app_date] => 2015-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 14770 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14734825 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/734825
Instruction group formation techniques for decode-time instruction optimization based on feedback Jun 8, 2015 Issued
Array ( [id] => 10793770 [patent_doc_number] => 20160139927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-19 [patent_title] => 'IDENTIFYING INSTRUCTIONS FOR DECODE-TIME INSTRUCTION OPTIMIZATION GROUPING IN VIEW OF CACHE BOUNDARIES' [patent_app_type] => utility [patent_app_number] => 14/734862 [patent_app_country] => US [patent_app_date] => 2015-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 14941 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14734862 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/734862
Identifying instructions for decode-time instruction optimization grouping in view of cache boundaries Jun 8, 2015 Issued
Array ( [id] => 10384110 [patent_doc_number] => 20150269118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-24 [patent_title] => 'Apparatus and Method for Processing an Instruction Matrix Specifying Parallel and Dependent Operations' [patent_app_type] => utility [patent_app_number] => 14/733827 [patent_app_country] => US [patent_app_date] => 2015-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 9397 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14733827 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/733827
Apparatus and method for processing an instruction matrix specifying parallel and dependent operations Jun 7, 2015 Issued
Array ( [id] => 11786602 [patent_doc_number] => 09396036 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-19 [patent_title] => 'System and method for limiting the impact of stragglers in large-scale parallel data processing' [patent_app_type] => utility [patent_app_number] => 14/727753 [patent_app_country] => US [patent_app_date] => 2015-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 18110 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 297 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14727753 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/727753
System and method for limiting the impact of stragglers in large-scale parallel data processing May 31, 2015 Issued
Array ( [id] => 10357354 [patent_doc_number] => 20150242359 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-27 [patent_title] => 'VERIFICATION OF DISTRIBUTED SYMMETRIC MULTI-PROCESSING SYSTEMS' [patent_app_type] => utility [patent_app_number] => 14/709491 [patent_app_country] => US [patent_app_date] => 2015-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6632 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14709491 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/709491
Verification of distributed symmetric multi-processing systems May 11, 2015 Issued
Array ( [id] => 10342364 [patent_doc_number] => 20150227370 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-13 [patent_title] => 'Processor, System, and Method for Efficient, High-Throughput Processing of Two-Dimensional, Interrelated Data Sets' [patent_app_type] => utility [patent_app_number] => 14/694066 [patent_app_country] => US [patent_app_date] => 2015-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 12674 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14694066 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/694066
Processor, system, and method for efficient, high-throughput processing of two-dimensional, interrelated data sets Apr 22, 2015 Issued
Array ( [id] => 10392921 [patent_doc_number] => 20150277928 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'SIMD PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/660253 [patent_app_country] => US [patent_app_date] => 2015-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 17201 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14660253 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/660253
SIMD processor Mar 16, 2015 Issued
Array ( [id] => 11069942 [patent_doc_number] => 20160266906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-15 [patent_title] => 'SYSTEM AND METHOD OF REISSUE PARKING FOR A MICROPROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/659372 [patent_app_country] => US [patent_app_date] => 2015-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6095 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14659372 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/659372
System and method of reissue parking for a microprocessor Mar 15, 2015 Issued
Array ( [id] => 10301135 [patent_doc_number] => 20150186135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'PARSING-ENHANCEMENT FACILITY' [patent_app_type] => utility [patent_app_number] => 14/645628 [patent_app_country] => US [patent_app_date] => 2015-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4823 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14645628 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/645628
Parsing-enhancement facility Mar 11, 2015 Issued
Array ( [id] => 10376531 [patent_doc_number] => 20150261538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-17 [patent_title] => 'DATA PROCESSING APPARATUS FOR EXECUTING AN ACCESS INSTRUCTION FOR N THREADS' [patent_app_type] => utility [patent_app_number] => 14/643018 [patent_app_country] => US [patent_app_date] => 2015-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11461 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14643018 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/643018
Data processing apparatus for executing an access instruction for N threads Mar 9, 2015 Issued
Array ( [id] => 10383956 [patent_doc_number] => 20150268963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-24 [patent_title] => 'EXECUTION OF DATA-PARALLEL PROGRAMS ON COARSE-GRAINED RECONFIGURABLE ARCHITECTURE HARDWARE' [patent_app_type] => utility [patent_app_number] => 14/642780 [patent_app_country] => US [patent_app_date] => 2015-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11305 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14642780 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/642780
EXECUTION OF DATA-PARALLEL PROGRAMS ON COARSE-GRAINED RECONFIGURABLE ARCHITECTURE HARDWARE Mar 9, 2015 Abandoned
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