Search

Stuart L. Hendrickson

Examiner (ID: 3648, Phone: (571)272-1351 , Office: P/1736 )

Most Active Art Unit
1736
Art Unit(s)
1206, 1793, 1754, 1103, 1736
Total Applications
2465
Issued Applications
1555
Pending Applications
254
Abandoned Applications
686

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11396952 [patent_doc_number] => 20170017488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-19 [patent_title] => 'PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO STORE CONSECUTIVE SOURCE ELEMENTS TO UNMASKED RESULT ELEMENTS WITH PROPAGATION TO MASKED RESULT ELEMENTS' [patent_app_type] => utility [patent_app_number] => 15/122005 [patent_app_country] => US [patent_app_date] => 2014-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 27402 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15122005 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/122005
Processors, methods, systems, and instructions to store consecutive source elements to unmasked result elements with propagation to masked result elements Mar 26, 2014 Issued
Array ( [id] => 10392914 [patent_doc_number] => 20150277921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'ADDRESS EXPANSION AND CONTRACTION IN A MULTITHREADING COMPUTER SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/226947 [patent_app_country] => US [patent_app_date] => 2014-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 13263 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14226947 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/226947
Address expansion and contraction in a multithreading computer system Mar 26, 2014 Issued
Array ( [id] => 10392913 [patent_doc_number] => 20150277920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'THREAD CONTEXT RESTORATION IN A MULTITHREADING COMPUTER SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/226911 [patent_app_country] => US [patent_app_date] => 2014-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 13728 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14226911 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/226911
Thread context restoration in a multithreading computer system Mar 26, 2014 Issued
Array ( [id] => 11465655 [patent_doc_number] => 09582285 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-28 [patent_title] => 'Speculative history forwarding in overriding branch predictors, and related circuits, methods, and computer-readable media' [patent_app_type] => utility [patent_app_number] => 14/223091 [patent_app_country] => US [patent_app_date] => 2014-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7313 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14223091 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/223091
Speculative history forwarding in overriding branch predictors, and related circuits, methods, and computer-readable media Mar 23, 2014 Issued
Array ( [id] => 10383952 [patent_doc_number] => 20150268959 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-24 [patent_title] => 'PHYSICAL REGISTER SCRUBBING IN A COMPUTER MICROPROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/221430 [patent_app_country] => US [patent_app_date] => 2014-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7412 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14221430 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/221430
PHYSICAL REGISTER SCRUBBING IN A COMPUTER MICROPROCESSOR Mar 20, 2014 Abandoned
Array ( [id] => 9758795 [patent_doc_number] => 20140289496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-25 [patent_title] => 'ENHANCED MACROSCALAR PREDICATE OPERATIONS' [patent_app_type] => utility [patent_app_number] => 14/218287 [patent_app_country] => US [patent_app_date] => 2014-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12982 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14218287 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/218287
Enhanced Macroscalar predicate operations Mar 17, 2014 Issued
Array ( [id] => 9758796 [patent_doc_number] => 20140289497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-25 [patent_title] => 'ENHANCED MACROSCALAR COMPARISON OPERATIONS' [patent_app_type] => utility [patent_app_number] => 14/218464 [patent_app_country] => US [patent_app_date] => 2014-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12947 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14218464 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/218464
ENHANCED MACROSCALAR COMPARISON OPERATIONS Mar 17, 2014 Abandoned
Array ( [id] => 9758794 [patent_doc_number] => 20140289495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-25 [patent_title] => 'ENHANCED PREDICATE REGISTERS' [patent_app_type] => utility [patent_app_number] => 14/218419 [patent_app_country] => US [patent_app_date] => 2014-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12915 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14218419 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/218419
Enhanced predicate registers having predicates corresponding to element widths Mar 17, 2014 Issued
Array ( [id] => 9758797 [patent_doc_number] => 20140289498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-25 [patent_title] => 'ENHANCED MACROSCALAR VECTOR OPERATIONS' [patent_app_type] => utility [patent_app_number] => 14/218497 [patent_app_country] => US [patent_app_date] => 2014-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 13051 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14218497 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/218497
ENHANCED MACROSCALAR VECTOR OPERATIONS Mar 17, 2014 Abandoned
Array ( [id] => 9758802 [patent_doc_number] => 20140289502 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-25 [patent_title] => 'ENHANCED VECTOR TRUE/FALSE PREDICATE-GENERATING INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 14/218475 [patent_app_country] => US [patent_app_date] => 2014-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 14347 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14218475 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/218475
ENHANCED VECTOR TRUE/FALSE PREDICATE-GENERATING INSTRUCTIONS Mar 17, 2014 Abandoned
Array ( [id] => 10376527 [patent_doc_number] => 20150261534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-17 [patent_title] => 'PACKED TWO SOURCE INTER-ELEMENT SHIFT MERGE PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 14/142738 [patent_app_country] => US [patent_app_date] => 2014-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 22601 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14142738 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/142738
Packed two source inter-element shift merge processors, methods, systems, and instructions Mar 12, 2014 Issued
Array ( [id] => 10507564 [patent_doc_number] => 09235440 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-12 [patent_title] => 'Managing job execution' [patent_app_type] => utility [patent_app_number] => 14/206310 [patent_app_country] => US [patent_app_date] => 2014-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6025 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14206310 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/206310
Managing job execution Mar 11, 2014 Issued
Array ( [id] => 14091777 [patent_doc_number] => 10241793 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-26 [patent_title] => Paralleizing loops in the presence of possible memory aliases [patent_app_type] => utility [patent_app_number] => 14/200788 [patent_app_country] => US [patent_app_date] => 2014-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7782 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14200788 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/200788
Paralleizing loops in the presence of possible memory aliases Mar 6, 2014 Issued
Array ( [id] => 11186638 [patent_doc_number] => 09418043 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-16 [patent_title] => 'Data speculation for array processors' [patent_app_type] => utility [patent_app_number] => 14/385953 [patent_app_country] => US [patent_app_date] => 2014-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4165 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14385953 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/385953
Data speculation for array processors Mar 6, 2014 Issued
Array ( [id] => 10357205 [patent_doc_number] => 20150242210 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-27 [patent_title] => 'Monitoring Vector Lane Duty Cycle For Dynamic Optimization' [patent_app_type] => utility [patent_app_number] => 14/190404 [patent_app_country] => US [patent_app_date] => 2014-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11350 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14190404 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/190404
Monitoring vector lane duty cycle for dynamic optimization Feb 25, 2014 Issued
Array ( [id] => 9513225 [patent_doc_number] => 20140149717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-29 [patent_title] => 'PERFORMING A MULTIPLY-MULTIPLY-ACCUMULATE INSTRUCTION' [patent_app_type] => utility [patent_app_number] => 14/169491 [patent_app_country] => US [patent_app_date] => 2014-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6808 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14169491 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/169491
Performing a multiply-multiply-accumulate instruction Jan 30, 2014 Issued
Array ( [id] => 9974199 [patent_doc_number] => 09021236 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-28 [patent_title] => 'Methods and apparatus for storing expanded width instructions in a VLIW memory for deferred execution' [patent_app_type] => utility [patent_app_number] => 14/151483 [patent_app_country] => US [patent_app_date] => 2014-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 30 [patent_no_of_words] => 9899 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14151483 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/151483
Methods and apparatus for storing expanded width instructions in a VLIW memory for deferred execution Jan 8, 2014 Issued
Array ( [id] => 9424121 [patent_doc_number] => 20140108772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-17 [patent_title] => 'Exploiting an Architected Last-Use Operand Indication in a System Operand Resource Pool' [patent_app_type] => utility [patent_app_number] => 14/138176 [patent_app_country] => US [patent_app_date] => 2013-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 22329 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14138176 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/138176
Exploiting an architected last-use operand indication in a system operand resource pool Dec 22, 2013 Issued
Array ( [id] => 9424117 [patent_doc_number] => 20140108768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-17 [patent_title] => 'Computer instructions for Activating and Deactivating Operands' [patent_app_type] => utility [patent_app_number] => 14/106892 [patent_app_country] => US [patent_app_date] => 2013-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 21783 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14106892 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/106892
Computer instructions for activating and deactivating operands Dec 15, 2013 Issued
Array ( [id] => 10117540 [patent_doc_number] => 09152425 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-06 [patent_title] => 'Mitigating instruction prediction latency with independently filtered presence predictors' [patent_app_type] => utility [patent_app_number] => 14/101417 [patent_app_country] => US [patent_app_date] => 2013-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6417 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14101417 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/101417
Mitigating instruction prediction latency with independently filtered presence predictors Dec 9, 2013 Issued
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