Search

Stuart L. Hendrickson

Examiner (ID: 3648, Phone: (571)272-1351 , Office: P/1736 )

Most Active Art Unit
1736
Art Unit(s)
1206, 1793, 1754, 1103, 1736
Total Applications
2465
Issued Applications
1555
Pending Applications
254
Abandoned Applications
686

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9714342 [patent_doc_number] => 08838943 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-16 [patent_title] => 'Rotate then operate on selected bits facility and instructions therefore' [patent_app_type] => utility [patent_app_number] => 12/840707 [patent_app_country] => US [patent_app_date] => 2010-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 16075 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12840707 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/840707
Rotate then operate on selected bits facility and instructions therefore Jul 20, 2010 Issued
Array ( [id] => 6461573 [patent_doc_number] => 20100281141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-04 [patent_title] => 'COMMUNICATION SYSTEM AND ITS METHOD AND COMMUNICATION APPARATUS AND ITS METHOD' [patent_app_type] => utility [patent_app_number] => 12/835450 [patent_app_country] => US [patent_app_date] => 2010-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 19208 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0281/20100281141.pdf [firstpage_image] =>[orig_patent_app_number] => 12835450 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/835450
Communication system and its method and communication apparatus and its method Jul 12, 2010 Issued
Array ( [id] => 8741130 [patent_doc_number] => 08412916 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-02 [patent_title] => 'Computing system having CPU and bridge operating using CPU frequency' [patent_app_type] => utility [patent_app_number] => 12/822258 [patent_app_country] => US [patent_app_date] => 2010-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3610 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12822258 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/822258
Computing system having CPU and bridge operating using CPU frequency Jun 23, 2010 Issued
Array ( [id] => 8998087 [patent_doc_number] => 08521992 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-27 [patent_title] => 'Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors' [patent_app_type] => utility [patent_app_number] => 12/822960 [patent_app_country] => US [patent_app_date] => 2010-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7725 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12822960 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/822960
Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors Jun 23, 2010 Issued
Array ( [id] => 9967813 [patent_doc_number] => 09015448 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-21 [patent_title] => 'Message broadcast with router bypassing' [patent_app_type] => utility [patent_app_number] => 12/817945 [patent_app_country] => US [patent_app_date] => 2010-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8454 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12817945 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/817945
Message broadcast with router bypassing Jun 16, 2010 Issued
Array ( [id] => 10644240 [patent_doc_number] => 09361109 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-07 [patent_title] => 'System and method to evaluate a data value as an instruction' [patent_app_type] => utility [patent_app_number] => 12/785551 [patent_app_country] => US [patent_app_date] => 2010-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5314 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12785551 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/785551
System and method to evaluate a data value as an instruction May 23, 2010 Issued
Array ( [id] => 8678620 [patent_doc_number] => 08386755 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-26 [patent_title] => 'Non-atomic scheduling of micro-operations to perform round instruction' [patent_app_type] => utility [patent_app_number] => 12/783769 [patent_app_country] => US [patent_app_date] => 2010-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6379 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12783769 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/783769
Non-atomic scheduling of micro-operations to perform round instruction May 19, 2010 Issued
Array ( [id] => 9089365 [patent_doc_number] => 08560812 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-15 [patent_title] => 'Device for executing an instruction using a target execution speed' [patent_app_type] => utility [patent_app_number] => 12/783958 [patent_app_country] => US [patent_app_date] => 2010-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 26 [patent_no_of_words] => 10057 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12783958 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/783958
Device for executing an instruction using a target execution speed May 19, 2010 Issued
Array ( [id] => 6615718 [patent_doc_number] => 20100293312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-18 [patent_title] => 'Network Communications Processor Architecture' [patent_app_type] => utility [patent_app_number] => 12/782379 [patent_app_country] => US [patent_app_date] => 2010-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11009 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0293/20100293312.pdf [firstpage_image] =>[orig_patent_app_number] => 12782379 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/782379
Network communications processor architecture May 17, 2010 Issued
Array ( [id] => 6272590 [patent_doc_number] => 20100299505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-25 [patent_title] => 'INSTRUCTION FUSION CALCULATION DEVICE AND METHOD FOR INSTRUCTION FUSION CALCULATION' [patent_app_type] => utility [patent_app_number] => 12/782618 [patent_app_country] => US [patent_app_date] => 2010-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6102 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0299/20100299505.pdf [firstpage_image] =>[orig_patent_app_number] => 12782618 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/782618
Instruction fusion calculation device and method for instruction fusion calculation May 17, 2010 Issued
Array ( [id] => 9077444 [patent_doc_number] => 08555036 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-10-08 [patent_title] => 'System and method for performing predicated selection of an output register' [patent_app_type] => utility [patent_app_number] => 12/780963 [patent_app_country] => US [patent_app_date] => 2010-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5290 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12780963 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/780963
System and method for performing predicated selection of an output register May 16, 2010 Issued
Array ( [id] => 6031520 [patent_doc_number] => 20110055530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'FAST REP STOS USING GRABLINE OPERATIONS' [patent_app_type] => utility [patent_app_number] => 12/781210 [patent_app_country] => US [patent_app_date] => 2010-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5272 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20110055530.pdf [firstpage_image] =>[orig_patent_app_number] => 12781210 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/781210
Fast REP STOS using grabline operations May 16, 2010 Issued
Array ( [id] => 6532323 [patent_doc_number] => 20100217958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-26 [patent_title] => 'Address calculation and select-and-insert instructions within data processing systems' [patent_app_type] => utility [patent_app_number] => 12/662734 [patent_app_country] => US [patent_app_date] => 2010-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6664 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20100217958.pdf [firstpage_image] =>[orig_patent_app_number] => 12662734 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/662734
Select-and-insert instruction within data processing systems Apr 29, 2010 Issued
Array ( [id] => 6554602 [patent_doc_number] => 20100205408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-12 [patent_title] => 'Speculative Region: Hardware Support for Selective Transactional Memory Access Annotation Using Instruction Prefix' [patent_app_type] => utility [patent_app_number] => 12/764024 [patent_app_country] => US [patent_app_date] => 2010-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6677 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20100205408.pdf [firstpage_image] =>[orig_patent_app_number] => 12764024 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/764024
Speculative Region: Hardware Support for Selective Transactional Memory Access Annotation Using Instruction Prefix Apr 19, 2010 Abandoned
Array ( [id] => 8923916 [patent_doc_number] => 08489865 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-07-16 [patent_title] => 'Device, system, and method for single thread command chaining instructions from multiple processor elements' [patent_app_type] => utility [patent_app_number] => 12/760822 [patent_app_country] => US [patent_app_date] => 2010-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6310 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12760822 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/760822
Device, system, and method for single thread command chaining instructions from multiple processor elements Apr 14, 2010 Issued
Array ( [id] => 8971709 [patent_doc_number] => 08510538 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-08-13 [patent_title] => 'System and method for limiting the impact of stragglers in large-scale parallel data processing' [patent_app_type] => utility [patent_app_number] => 12/759637 [patent_app_country] => US [patent_app_date] => 2010-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 18173 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12759637 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/759637
System and method for limiting the impact of stragglers in large-scale parallel data processing Apr 12, 2010 Issued
Array ( [id] => 8861476 [patent_doc_number] => 08464030 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-11 [patent_title] => 'Instruction cracking and issue shortening based on instruction base fields, index fields, operand fields, and various other instruction text bits' [patent_app_type] => utility [patent_app_number] => 12/757330 [patent_app_country] => US [patent_app_date] => 2010-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 29 [patent_no_of_words] => 6952 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 334 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12757330 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/757330
Instruction cracking and issue shortening based on instruction base fields, index fields, operand fields, and various other instruction text bits Apr 8, 2010 Issued
12/756806 HANDLING OF INITIALLY UNEXECUTABLE INSTRUCTIONS Apr 7, 2010 Abandoned
Array ( [id] => 8608589 [patent_doc_number] => 20130013902 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-10 [patent_title] => 'DYNAMICALLY RECONFIGURABLE PROCESSOR AND METHOD OF OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/635307 [patent_app_country] => US [patent_app_date] => 2010-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 10957 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13635307 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/635307
DYNAMICALLY RECONFIGURABLE PROCESSOR AND METHOD OF OPERATING THE SAME Apr 5, 2010 Abandoned
Array ( [id] => 5976410 [patent_doc_number] => 20110153983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-23 [patent_title] => 'Gathering and Scattering Multiple Data Elements' [patent_app_type] => utility [patent_app_number] => 12/644440 [patent_app_country] => US [patent_app_date] => 2009-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6841 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20110153983.pdf [firstpage_image] =>[orig_patent_app_number] => 12644440 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/644440
Gathering and scattering multiple data elements Dec 21, 2009 Issued
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