Search

Stuart L. Hendrickson

Examiner (ID: 3648, Phone: (571)272-1351 , Office: P/1736 )

Most Active Art Unit
1736
Art Unit(s)
1206, 1793, 1754, 1103, 1736
Total Applications
2465
Issued Applications
1555
Pending Applications
254
Abandoned Applications
686

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19015232 [patent_doc_number] => 11922166 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => Vector SIMD VLIW data path architecture [patent_app_type] => utility [patent_app_number] => 18/097552 [patent_app_country] => US [patent_app_date] => 2023-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 25 [patent_no_of_words] => 10397 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18097552 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/097552
Vector SIMD VLIW data path architecture Jan 16, 2023 Issued
Array ( [id] => 19251053 [patent_doc_number] => 20240202043 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => DYNAMIC SUBTASK CREATION AND EXECUTION IN PROCESSING PLATFORMS [patent_app_type] => utility [patent_app_number] => 18/083127 [patent_app_country] => US [patent_app_date] => 2022-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14164 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18083127 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/083127
Dynamic subtask creation and execution in processing platforms Dec 15, 2022 Issued
Array ( [id] => 19251012 [patent_doc_number] => 20240202002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => METHODS AND APPARATUSES FOR INSTRUCTIONS INCLUDING A MISPREDICTION HANDLING HINT TO REDUCE A BRANCH MISPREDICTION PENALTY [patent_app_type] => utility [patent_app_number] => 18/067577 [patent_app_country] => US [patent_app_date] => 2022-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23282 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18067577 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/067577
METHODS AND APPARATUSES FOR INSTRUCTIONS INCLUDING A MISPREDICTION HANDLING HINT TO REDUCE A BRANCH MISPREDICTION PENALTY Dec 15, 2022 Pending
Array ( [id] => 18325876 [patent_doc_number] => 20230124004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => METHOD FOR HANDLING EXCEPTION OR INTERRUPT IN HETEROGENEOUS INSTRUCTION SET ARCHITECTURE AND APPARATUS [patent_app_type] => utility [patent_app_number] => 18/064543 [patent_app_country] => US [patent_app_date] => 2022-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18951 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18064543 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/064543
Method for handling exception or interrupt in heterogeneous instruction set architecture and apparatus Dec 11, 2022 Issued
Array ( [id] => 19189850 [patent_doc_number] => 20240168763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => APPLICATION PROGRAMMING INTERFACE TO INDICATE OPERATIONS TO BE PERFORMED BY CORRESPONDING STREAMING MULTIPROCESSORS [patent_app_type] => utility [patent_app_number] => 18/072300 [patent_app_country] => US [patent_app_date] => 2022-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 66152 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18072300 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/072300
APPLICATION PROGRAMMING INTERFACE TO INDICATE OPERATIONS TO BE PERFORMED BY CORRESPONDING STREAMING MULTIPROCESSORS Nov 29, 2022 Pending
Array ( [id] => 18606803 [patent_doc_number] => 11748270 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => Tracking streaming engine vector predicates to control processor execution [patent_app_type] => utility [patent_app_number] => 17/990812 [patent_app_country] => US [patent_app_date] => 2022-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 37 [patent_no_of_words] => 29556 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17990812 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/990812
Tracking streaming engine vector predicates to control processor execution Nov 20, 2022 Issued
Array ( [id] => 19189851 [patent_doc_number] => 20240168764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => SUPPORTING AND LOAD BALANCING MULTIPLE DOUBLE PRECISION PIPELINES IN A GRAPHICS ENVIRONMENT [patent_app_type] => utility [patent_app_number] => 18/056820 [patent_app_country] => US [patent_app_date] => 2022-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 50721 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18056820 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/056820
SUPPORTING AND LOAD BALANCING MULTIPLE DOUBLE PRECISION PIPELINES IN A GRAPHICS ENVIRONMENT Nov 17, 2022 Pending
Array ( [id] => 18393855 [patent_doc_number] => 20230162075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => APPARATUS AND METHOD FOR SCALABLE QUBIT ADDRESSING [patent_app_type] => utility [patent_app_number] => 17/988994 [patent_app_country] => US [patent_app_date] => 2022-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12741 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17988994 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/988994
Apparatus and method for scalable qubit addressing Nov 16, 2022 Issued
Array ( [id] => 19159652 [patent_doc_number] => 20240152359 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => ENSURING FAIRNESS FOR TRY SPIN LOCK [patent_app_type] => utility [patent_app_number] => 17/981183 [patent_app_country] => US [patent_app_date] => 2022-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6956 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17981183 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/981183
ENSURING FAIRNESS FOR TRY SPIN LOCK Nov 3, 2022 Pending
Array ( [id] => 19198206 [patent_doc_number] => 11995445 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-28 [patent_title] => Assignment of microprocessor register tags at issue time [patent_app_type] => utility [patent_app_number] => 18/051175 [patent_app_country] => US [patent_app_date] => 2022-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7825 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18051175 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/051175
Assignment of microprocessor register tags at issue time Oct 30, 2022 Issued
Array ( [id] => 19398860 [patent_doc_number] => 12073231 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-27 [patent_title] => Fractional force-quit for reconfigurable processors [patent_app_type] => utility [patent_app_number] => 17/974496 [patent_app_country] => US [patent_app_date] => 2022-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 17524 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17974496 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/974496
Fractional force-quit for reconfigurable processors Oct 25, 2022 Issued
Array ( [id] => 20265774 [patent_doc_number] => 12436765 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Data processing apparatus, chip, and data processing method [patent_app_type] => utility [patent_app_number] => 18/049483 [patent_app_country] => US [patent_app_date] => 2022-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2352 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18049483 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/049483
Data processing apparatus, chip, and data processing method Oct 24, 2022 Issued
Array ( [id] => 19725779 [patent_doc_number] => 20250028530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => TECHNIQUES FOR CONTROLLING VECTOR PROCESSING OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/711220 [patent_app_country] => US [patent_app_date] => 2022-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10733 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18711220 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/711220
TECHNIQUES FOR CONTROLLING VECTOR PROCESSING OPERATIONS Oct 17, 2022 Pending
Array ( [id] => 19313515 [patent_doc_number] => 12039331 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-16 [patent_title] => Instructions and logic to perform floating point and integer operations for machine learning [patent_app_type] => utility [patent_app_number] => 17/967283 [patent_app_country] => US [patent_app_date] => 2022-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 51 [patent_no_of_words] => 39550 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17967283 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/967283
Instructions and logic to perform floating point and integer operations for machine learning Oct 16, 2022 Issued
Array ( [id] => 18957354 [patent_doc_number] => 20240045681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => 8-BIT FLOATING POINT COMPARISON INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 17/958367 [patent_app_country] => US [patent_app_date] => 2022-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18522 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17958367 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/958367
8-BIT FLOATING POINT COMPARISON INSTRUCTIONS Sep 30, 2022 Pending
Array ( [id] => 19084738 [patent_doc_number] => 20240111539 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => DEVICE, METHOD AND SYSTEM TO DETERMINE A MODE OF PROCESSOR OPERATION BASED ON PAGE TABLE METADATA [patent_app_type] => utility [patent_app_number] => 17/957969 [patent_app_country] => US [patent_app_date] => 2022-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20109 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17957969 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/957969
DEVICE, METHOD AND SYSTEM TO DETERMINE A MODE OF PROCESSOR OPERATION BASED ON PAGE TABLE METADATA Sep 29, 2022 Pending
Array ( [id] => 20595275 [patent_doc_number] => 12578992 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-17 [patent_title] => Work graph scheduler implementation [patent_app_type] => utility [patent_app_number] => 17/936788 [patent_app_country] => US [patent_app_date] => 2022-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 0 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17936788 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/936788
Work graph scheduler implementation Sep 28, 2022 Issued
Array ( [id] => 18147859 [patent_doc_number] => 20230021716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => NEURAL NETWORK MODEL COMPUTING CHIP, METHOD, AND APPARATUS, DEVICE, AND MEDIUM [patent_app_type] => utility [patent_app_number] => 17/954163 [patent_app_country] => US [patent_app_date] => 2022-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11376 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17954163 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/954163
NEURAL NETWORK MODEL COMPUTING CHIP, METHOD, AND APPARATUS, DEVICE, AND MEDIUM Sep 26, 2022 Pending
Array ( [id] => 19719361 [patent_doc_number] => 12204900 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Predicates for processing-in-memory [patent_app_type] => utility [patent_app_number] => 17/953142 [patent_app_country] => US [patent_app_date] => 2022-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7292 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17953142 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/953142
Predicates for processing-in-memory Sep 25, 2022 Issued
Array ( [id] => 19780536 [patent_doc_number] => 12229570 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => Block data load with transpose into memory [patent_app_type] => utility [patent_app_number] => 17/952270 [patent_app_country] => US [patent_app_date] => 2022-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4240 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17952270 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/952270
Block data load with transpose into memory Sep 24, 2022 Issued
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