Search

Suchin Parihar

Examiner (ID: 4041, Phone: (571)272-6210 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851, 2872
Total Applications
1418
Issued Applications
1198
Pending Applications
84
Abandoned Applications
154

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18680660 [patent_doc_number] => 20230318322 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => CHARGING DEVICE AND CHARGING SYSTEM [patent_app_type] => utility [patent_app_number] => 18/312734 [patent_app_country] => US [patent_app_date] => 2023-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6845 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18312734 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/312734
CHARGING DEVICE AND CHARGING SYSTEM May 4, 2023 Pending
Array ( [id] => 18957099 [patent_doc_number] => 20240045426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => SYSTEMS AND METHODS FOR SAFE AND RELIABLE AUTONOMOUS VEHICLES [patent_app_type] => utility [patent_app_number] => 18/143360 [patent_app_country] => US [patent_app_date] => 2023-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 65275 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18143360 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/143360
SYSTEMS AND METHODS FOR SAFE AND RELIABLE AUTONOMOUS VEHICLES May 3, 2023 Pending
Array ( [id] => 20689661 [patent_doc_number] => 12619812 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-05 [patent_title] => Automatically generating method, automatically generating system for generating simulation circuit and computer readable recording medium [patent_app_type] => utility [patent_app_number] => 18/309836 [patent_app_country] => US [patent_app_date] => 2023-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 0 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 316 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18309836 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/309836
Automatically generating method, automatically generating system for generating simulation circuit and computer readable recording medium Apr 30, 2023 Issued
Array ( [id] => 18585000 [patent_doc_number] => 20230267264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => Hotspot Avoidance Method of Manufacturing Integrated Circuits [patent_app_type] => utility [patent_app_number] => 18/308916 [patent_app_country] => US [patent_app_date] => 2023-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7440 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18308916 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/308916
Hotspot avoidance method of manufacturing integrated circuits Apr 27, 2023 Issued
Array ( [id] => 19529911 [patent_doc_number] => 20240353813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => PROCESS FOR GENERATING PHYSICAL IMPLEMENTATION GUIDANCE DURING THE SYNTHESIS OF A NETWORK-ON-CHIP [patent_app_type] => utility [patent_app_number] => 18/305382 [patent_app_country] => US [patent_app_date] => 2023-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9933 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18305382 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/305382
PROCESS FOR GENERATING PHYSICAL IMPLEMENTATION GUIDANCE DURING THE SYNTHESIS OF A NETWORK-ON-CHIP Apr 23, 2023 Pending
Array ( [id] => 18787913 [patent_doc_number] => 20230376292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => COMPILE TIME LOGIC FOR DETECTING AND RESOLVING MEMORY LAYOUT CONFLICTS [patent_app_type] => utility [patent_app_number] => 18/136321 [patent_app_country] => US [patent_app_date] => 2023-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17864 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18136321 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/136321
COMPILE TIME LOGIC FOR DETECTING AND RESOLVING MEMORY LAYOUT CONFLICTS Apr 17, 2023 Pending
Array ( [id] => 18556993 [patent_doc_number] => 20230255012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => METAL ISOLATION TESTING IN THE CONTEXT OF MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 18/300513 [patent_app_country] => US [patent_app_date] => 2023-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6961 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18300513 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/300513
METAL ISOLATION TESTING IN THE CONTEXT OF MEMORY CELLS Apr 13, 2023 Pending
Array ( [id] => 18807917 [patent_doc_number] => 20230382250 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => ELECTRIC CHARGING STATION FOR AN ELECTRIC VEHICLE AND A METHOD FOR ITS USE [patent_app_type] => utility [patent_app_number] => 18/130064 [patent_app_country] => US [patent_app_date] => 2023-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20811 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18130064 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/130064
Electric charging station for an electric vehicle and a method for its use Apr 2, 2023 Issued
Array ( [id] => 19482514 [patent_doc_number] => 20240330556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => LOCATION AWARE TIMING ANALYSIS OF A DIGITAL INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/192839 [patent_app_country] => US [patent_app_date] => 2023-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5964 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18192839 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/192839
LOCATION AWARE TIMING ANALYSIS OF A DIGITAL INTEGRATED CIRCUIT Mar 29, 2023 Pending
Array ( [id] => 18524013 [patent_doc_number] => 20230234670 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-27 [patent_title] => BICYCLE DRIVE SYSTEM, BICYCLE DRIVE UNIT, AND BICYCLE BATTERY UNIT [patent_app_type] => utility [patent_app_number] => 18/127228 [patent_app_country] => US [patent_app_date] => 2023-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13643 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18127228 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/127228
BICYCLE DRIVE SYSTEM, BICYCLE DRIVE UNIT, AND BICYCLE BATTERY UNIT Mar 27, 2023 Pending
Array ( [id] => 18532159 [patent_doc_number] => 20230237231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-27 [patent_title] => Modular Compilation Flows for a Programmable Logic Device [patent_app_type] => utility [patent_app_number] => 18/191785 [patent_app_country] => US [patent_app_date] => 2023-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8496 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18191785 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/191785
Modular Compilation Flows for a Programmable Logic Device Mar 27, 2023 Pending
Array ( [id] => 20828572 [patent_doc_number] => 12682143 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-07-14 [patent_title] => Identifying RTL code that can be a source of verification complexity for downstream equivalence checkers and generating recommendations to improve runtime of equivalence checkers [patent_app_type] => utility [patent_app_number] => 18/126164 [patent_app_country] => US [patent_app_date] => 2023-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 3167 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18126164 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/126164
Identifying RTL code that can be a source of verification complexity for downstream equivalence checkers and generating recommendations to improve runtime of equivalence checkers Mar 23, 2023 Issued
Array ( [id] => 18925800 [patent_doc_number] => 20240028804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => OPERATING METHOD OF ELECTRONIC DEVICE SIMULATING DESIGN OF INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/126128 [patent_app_country] => US [patent_app_date] => 2023-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8216 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18126128 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/126128
OPERATING METHOD OF ELECTRONIC DEVICE SIMULATING DESIGN OF INTEGRATED CIRCUIT Mar 23, 2023 Pending
Array ( [id] => 19420146 [patent_doc_number] => 20240296269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => MODELING OF FOUR-STATE-AWARE MEMORIES IN AN EMULATION SYSTEM [patent_app_type] => utility [patent_app_number] => 18/178463 [patent_app_country] => US [patent_app_date] => 2023-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13944 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18178463 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/178463
MODELING OF FOUR-STATE-AWARE MEMORIES IN AN EMULATION SYSTEM Mar 2, 2023 Pending
Array ( [id] => 19420151 [patent_doc_number] => 20240296274 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => LOGIC CELL PLACEMENT MECHANISMS FOR IMPROVED CLOCK ON-CHIP VARIATION [patent_app_type] => utility [patent_app_number] => 18/178375 [patent_app_country] => US [patent_app_date] => 2023-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13934 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18178375 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/178375
LOGIC CELL PLACEMENT MECHANISMS FOR IMPROVED CLOCK ON-CHIP VARIATION Mar 2, 2023 Pending
Array ( [id] => 18904960 [patent_doc_number] => 20240020445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => AUTOMATED ARTIFICIAL INTELLIGENCE BASED CIRCUIT AND CIRCUIT BOARD DESIGN [patent_app_type] => utility [patent_app_number] => 18/174492 [patent_app_country] => US [patent_app_date] => 2023-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13523 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18174492 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/174492
AUTOMATED ARTIFICIAL INTELLIGENCE BASED CIRCUIT AND CIRCUIT BOARD DESIGN Feb 23, 2023 Issued
Array ( [id] => 18470790 [patent_doc_number] => 20230205076 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => RESIST AND ETCH MODELING [patent_app_type] => utility [patent_app_number] => 18/174293 [patent_app_country] => US [patent_app_date] => 2023-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15775 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18174293 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/174293
RESIST AND ETCH MODELING Feb 23, 2023 Pending
Array ( [id] => 18614760 [patent_doc_number] => 20230281497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => QUANTUM CIRCUIT OPTIMIZATION USING WINDOWED QUANTUM ARITHMETIC [patent_app_type] => utility [patent_app_number] => 18/111413 [patent_app_country] => US [patent_app_date] => 2023-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10334 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18111413 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/111413
Quantum circuit optimization using windowed quantum arithmetic Feb 16, 2023 Issued
Array ( [id] => 19036794 [patent_doc_number] => 20240086609 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => INTEGRATED CIRCUIT DESIGN METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT [patent_app_type] => utility [patent_app_number] => 18/170111 [patent_app_country] => US [patent_app_date] => 2023-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24211 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18170111 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/170111
INTEGRATED CIRCUIT DESIGN METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT Feb 15, 2023 Pending
Array ( [id] => 18942298 [patent_doc_number] => 20240037437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => QUANTUM INFORMATION PROCESSING DEVICE AND QUANTUM INFORMATION PROCESSING SYSTEM [patent_app_type] => utility [patent_app_number] => 18/109358 [patent_app_country] => US [patent_app_date] => 2023-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3469 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18109358 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/109358
QUANTUM INFORMATION PROCESSING DEVICE AND QUANTUM INFORMATION PROCESSING SYSTEM Feb 13, 2023 Issued
Menu