Suchin Parihar

Array ( [id] => 15297941 [patent_doc_number] => 20190392106 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => OPTIMIZING LIBRARY CELLS WITH WIRING IN METALLIZATION LAYERS [patent_app_type] => utility [patent_app_number] => 16/014287 [patent_app_country] => US [patent_app_date] => 2018-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9257 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16014287 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15297949 [patent_doc_number] => 20190392110 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => MODIFYING LAYOUT BY REMOVING FILL CELL FROM FILL-DENSE REGIONS AND INSERTING DUPLICATE IN TARGET FILL REGION [patent_app_type] => utility [patent_app_number] => 16/013403 [patent_app_country] => US [patent_app_date] => 2018-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11174 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16013403 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16291384 [patent_doc_number] => 10768227 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-08 [patent_title] => Systems and methods for analyzing failure rates due to soft/hard errors in the design of a digital electronic device [patent_app_type] => utility [patent_app_number] => 16/013931 [patent_app_country] => US [patent_app_date] => 2018-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3680 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16013931 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13797771 [patent_doc_number] => 20190012424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-10 [patent_title] => SYSTEM AND METHOD FOR ELECTRONIC AUTOMATED PRINTED CIRCUIT DESIGN [patent_app_type] => utility [patent_app_number] => 16/011837 [patent_app_country] => US [patent_app_date] => 2018-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13186 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16011837 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16088973 [patent_doc_number] => 20200198473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => METHOD FOR DETECTING A PLUG-IN OPERATION [patent_app_type] => utility [patent_app_number] => 16/622835 [patent_app_country] => US [patent_app_date] => 2018-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3944 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16622835 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13615243 [patent_doc_number] => 20180359173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-13 [patent_title] => INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 16/000936 [patent_app_country] => US [patent_app_date] => 2018-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10881 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16000936 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17540550 [patent_doc_number] => 11305658 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-19 [patent_title] => Charger for charging an electric vehicle [patent_app_type] => utility [patent_app_number] => 16/617897 [patent_app_country] => US [patent_app_date] => 2018-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 14737 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16617897 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15215495 [patent_doc_number] => 20190370434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => AUTOMATIC GENERATION OF VIA PATTERNS WITH COORDINATE-BASED RECURRENT NEURAL NETWORK (RNN) [patent_app_type] => utility [patent_app_number] => 15/994396 [patent_app_country] => US [patent_app_date] => 2018-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6073 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15994396 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15215489 [patent_doc_number] => 20190370431 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => COORDINATES-BASED GENERATIVE ADVERSARIAL NETWORKS FOR GENERATING SYNTHETIC PHYSICAL DESIGN LAYOUT PATTERNS [patent_app_type] => utility [patent_app_number] => 15/994598 [patent_app_country] => US [patent_app_date] => 2018-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8650 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15994598 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15215493 [patent_doc_number] => 20190370433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => Method of Redistribution Layer Routing for 2.5-Dimensional Integrated Circuit Packages [patent_app_type] => utility [patent_app_number] => 15/993606 [patent_app_country] => US [patent_app_date] => 2018-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8435 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15993606 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15215497 [patent_doc_number] => 20190370435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => GENERATING SYNTHETIC LAYOUT PATTERNS BY FEEDFORWARD NEURAL NETWORK BASED VARIATIONAL AUTOENCODERS [patent_app_type] => utility [patent_app_number] => 15/994461 [patent_app_country] => US [patent_app_date] => 2018-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6254 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15994461 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13595971 [patent_doc_number] => 20180349534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => OPTIMUM STAGE NUMBER CALCULATION METHOD, INFORMATION PROCESSING APPARATUS, AND RECORDING MEDIUM [patent_app_type] => utility [patent_app_number] => 15/992334 [patent_app_country] => US [patent_app_date] => 2018-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6495 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15992334 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13569513 [patent_doc_number] => 20180336304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-22 [patent_title] => METHOD FOR COMPRESSION OF EMULATION TIME LINE IN PRESENCE OF DYNAMIC RE-PROGRAMMING OF CLOCKS [patent_app_type] => utility [patent_app_number] => 15/982997 [patent_app_country] => US [patent_app_date] => 2018-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10619 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15982997 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15578741 [patent_doc_number] => 10579757 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-03-03 [patent_title] => Calculating and extracting joule-heating and self-heat induced temperature on wire segments for chip reliability [patent_app_type] => utility [patent_app_number] => 15/979583 [patent_app_country] => US [patent_app_date] => 2018-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 6074 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 15 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15979583 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16144703 [patent_doc_number] => 10705420 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-07 [patent_title] => Mask bias approximation [patent_app_type] => utility [patent_app_number] => 15/979751 [patent_app_country] => US [patent_app_date] => 2018-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9928 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15979751 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16146255 [patent_doc_number] => 10706199 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-07-07 [patent_title] => Graphical user interface for interactive macro-cell placement [patent_app_type] => utility [patent_app_number] => 15/979171 [patent_app_country] => US [patent_app_date] => 2018-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7627 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15979171 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14996871 [patent_doc_number] => 20190317393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-17 [patent_title] => MASK AND METHOD OF FORMING PATTERN [patent_app_type] => utility [patent_app_number] => 15/978215 [patent_app_country] => US [patent_app_date] => 2018-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4776 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15978215 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13417931 [patent_doc_number] => 20180260508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => Method And Apparatus For Modeling Delays In Emulation [patent_app_type] => utility [patent_app_number] => 15/979194 [patent_app_country] => US [patent_app_date] => 2018-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6526 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15979194 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15373941 [patent_doc_number] => 10528691 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-01-07 [patent_title] => Method and system for automated selection of a subset of plurality of validation tests [patent_app_type] => utility [patent_app_number] => 15/978527 [patent_app_country] => US [patent_app_date] => 2018-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4308 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15978527 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15578751 [patent_doc_number] => 10579762 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-03 [patent_title] => High-level synthesis (HLS) method and apparatus to specify pipeline and spatial parallelism in computer hardware [patent_app_type] => utility [patent_app_number] => 15/977874 [patent_app_country] => US [patent_app_date] => 2018-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 7474 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15977874 [rel_patent_id] =>[rel_patent_doc_number] =>)