Suchin Parihar

Array ( [id] => 11518034 [patent_doc_number] => 20170085107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'Energy Storage Devices and Methods for Fast Charging of Energy Storage Devices at Very Low Temperatures' [patent_app_type] => utility [patent_app_number] => 15/049043 [patent_app_country] => US [patent_app_date] => 2016-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 12418 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15049043 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14197937 [patent_doc_number] => 10266060 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-23 [patent_title] => SS-L wireless power transfer compensation circuit [patent_app_type] => utility [patent_app_number] => 15/047868 [patent_app_country] => US [patent_app_date] => 2016-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 3934 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15047868 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12324639 [patent_doc_number] => 09944192 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-17 [patent_title] => Electric vehicle charging station system and method of use [patent_app_type] => utility [patent_app_number] => 15/048307 [patent_app_country] => US [patent_app_date] => 2016-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 28 [patent_no_of_words] => 20297 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15048307 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15489207 [patent_doc_number] => 10559971 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-11 [patent_title] => Wirelessly chargeable battery apparatus [patent_app_type] => utility [patent_app_number] => 15/048982 [patent_app_country] => US [patent_app_date] => 2016-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 44 [patent_no_of_words] => 11741 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15048982 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13031405 [patent_doc_number] => 10038332 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-07-31 [patent_title] => Systems and methods of wireless power charging through multiple receiving devices [patent_app_type] => utility [patent_app_number] => 15/047831 [patent_app_country] => US [patent_app_date] => 2016-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 38 [patent_no_of_words] => 20419 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15047831 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11049306 [patent_doc_number] => 20160246265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-25 [patent_title] => 'ELECTRONIC DEVICE AND METHOD OF CORRECTING POSITION THEREOF' [patent_app_type] => utility [patent_app_number] => 15/046927 [patent_app_country] => US [patent_app_date] => 2016-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 13473 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15046927 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12108345 [patent_doc_number] => 09864830 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-01-09 [patent_title] => 'Method and apparatus for placement and routing of circuit designs' [patent_app_type] => utility [patent_app_number] => 15/040814 [patent_app_country] => US [patent_app_date] => 2016-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6619 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15040814 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12194842 [patent_doc_number] => 09898573 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-20 [patent_title] => 'Rule and process assumption co-optimization using feature-specific layout-based statistical analyses' [patent_app_type] => utility [patent_app_number] => 15/040453 [patent_app_country] => US [patent_app_date] => 2016-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8257 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15040453 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11931852 [patent_doc_number] => 09798852 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-24 [patent_title] => 'Methods of design rule checking of circuit designs' [patent_app_type] => utility [patent_app_number] => 15/040235 [patent_app_country] => US [patent_app_date] => 2016-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 7080 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15040235 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12167774 [patent_doc_number] => 09886543 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-06 [patent_title] => 'Method providing for asymmetric pupil configuration for an extreme ultraviolet lithography process' [patent_app_type] => utility [patent_app_number] => 15/040049 [patent_app_country] => US [patent_app_date] => 2016-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 10190 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15040049 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12967297 [patent_doc_number] => 09875327 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-23 [patent_title] => Timing violation resilient asynchronous template [patent_app_type] => utility [patent_app_number] => 15/016059 [patent_app_country] => US [patent_app_date] => 2016-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 22 [patent_no_of_words] => 13932 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15016059 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10802753 [patent_doc_number] => 20160148910 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-26 [patent_title] => 'Semiconductor Device Having Plural Memory Chip' [patent_app_type] => utility [patent_app_number] => 15/010930 [patent_app_country] => US [patent_app_date] => 2016-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6676 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15010930 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12088448 [patent_doc_number] => 09842178 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-12 [patent_title] => 'Systems and methods for binding mismatched schematic and layout design hierarchy' [patent_app_type] => utility [patent_app_number] => 14/981422 [patent_app_country] => US [patent_app_date] => 2015-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8000 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14981422 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11494585 [patent_doc_number] => 20170068770 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-09 [patent_title] => 'VERIFICATION METHOD OF MASK PATTERN, MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE AND NONTRANSITORY COMPUTER READABLE MEDIUM STORING A MASK PATTERN VERIFICATION PROGRAM' [patent_app_type] => utility [patent_app_number] => 14/979668 [patent_app_country] => US [patent_app_date] => 2015-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6135 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14979668 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13920127 [patent_doc_number] => 10204187 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-02-12 [patent_title] => Method and system for implementing data reduction for waveform data [patent_app_type] => utility [patent_app_number] => 14/981488 [patent_app_country] => US [patent_app_date] => 2015-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 7370 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14981488 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11709277 [patent_doc_number] => 20170177775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'SYSTEMS AND METHODS FOR TRACKING CHANGES TO AND IDENTIFYING LAYERS OF INTERGRATED CIRCUIT DEVICES' [patent_app_type] => utility [patent_app_number] => 14/976707 [patent_app_country] => US [patent_app_date] => 2015-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10130 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14976707 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12955069 [patent_doc_number] => 09837850 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-05 [patent_title] => Non-contact charger system, control device, wireless communication device, and non-contact charging device [patent_app_type] => utility [patent_app_number] => 14/976729 [patent_app_country] => US [patent_app_date] => 2015-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4512 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14976729 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11709279 [patent_doc_number] => 20170177778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'EDITING A NoC TOPOLOGY ON TOP OF A FLOORPLAN' [patent_app_type] => utility [patent_app_number] => 14/975844 [patent_app_country] => US [patent_app_date] => 2015-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 4819 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14975844 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11709285 [patent_doc_number] => 20170177784 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'INCREMENTAL PARASITIC EXTRACTION FOR COUPLED TIMING AND POWER OPTIMIZATION' [patent_app_type] => utility [patent_app_number] => 14/973893 [patent_app_country] => US [patent_app_date] => 2015-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6350 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14973893 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13975061 [patent_doc_number] => 10216887 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-02-26 [patent_title] => Methods, systems, and computer program products for implementing an electronic design with time varying resistors in power gating analysis [patent_app_type] => utility [patent_app_number] => 14/974570 [patent_app_country] => US [patent_app_date] => 2015-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 14488 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14974570 [rel_patent_id] =>[rel_patent_doc_number] =>)