Search

Suchin Parihar

Examiner (ID: 4481)

Most Active Art Unit
2851
Art Unit(s)
2825, 2851, 2872
Total Applications
1385
Issued Applications
1167
Pending Applications
109
Abandoned Applications
148

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10065034 [patent_doc_number] => 09103878 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-11 [patent_title] => 'Method for scan testing three-dimensional chip' [patent_app_type] => utility [patent_app_number] => 14/394296 [patent_app_country] => US [patent_app_date] => 2013-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6562 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14394296 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/394296
Method for scan testing three-dimensional chip Apr 16, 2013 Issued
Array ( [id] => 9746613 [patent_doc_number] => 20140282332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'FAULT INJECTION OF FINFET DEVICES' [patent_app_type] => utility [patent_app_number] => 13/864725 [patent_app_country] => US [patent_app_date] => 2013-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5928 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13864725 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/864725
Fault injection of finFET devices Apr 16, 2013 Issued
Array ( [id] => 9110087 [patent_doc_number] => 20130283219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-24 [patent_title] => 'METHOD AND SYSTEM FOR FORMING PATTERNS USING CHARGED PARTICLE BEAM LITHOGRAPHY' [patent_app_type] => utility [patent_app_number] => 13/862475 [patent_app_country] => US [patent_app_date] => 2013-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11448 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13862475 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/862475
Method and system for forming patterns using charged particle beam lithography Apr 14, 2013 Issued
Array ( [id] => 9282985 [patent_doc_number] => 20140032953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-30 [patent_title] => 'BATTERY CHARGE SYSTEM AND METHOD CAPABLE OF OPERATING IN DIFFERENT CONFIGURATIONS' [patent_app_type] => utility [patent_app_number] => 13/850977 [patent_app_country] => US [patent_app_date] => 2013-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5602 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13850977 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/850977
Battery charge system and method capable of operating in different configurations Mar 25, 2013 Issued
Array ( [id] => 9758994 [patent_doc_number] => 20140289695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-25 [patent_title] => 'EVALUATION OF PIN GEOMETRY ACCESSIBILITY IN A LAYER OF CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/849575 [patent_app_country] => US [patent_app_date] => 2013-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7721 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13849575 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/849575
Evaluation of pin geometry accessibility in a layer of circuit Mar 24, 2013 Issued
Array ( [id] => 9623431 [patent_doc_number] => 08793626 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-29 [patent_title] => 'Computational lithography with feature upsizing' [patent_app_type] => utility [patent_app_number] => 13/849195 [patent_app_country] => US [patent_app_date] => 2013-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4201 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13849195 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/849195
Computational lithography with feature upsizing Mar 21, 2013 Issued
Array ( [id] => 9289533 [patent_doc_number] => 08645891 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-04 [patent_title] => 'Device for and method of generating wiring data, and imaging system' [patent_app_type] => utility [patent_app_number] => 13/835398 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 15756 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13835398 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/835398
Device for and method of generating wiring data, and imaging system Mar 14, 2013 Issued
Array ( [id] => 10046774 [patent_doc_number] => 09087174 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-07-21 [patent_title] => 'Methods, systems, and articles of manufacture for implementing multiple-patterning-aware design rule check for electronic designs' [patent_app_type] => utility [patent_app_number] => 13/840567 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 12208 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13840567 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/840567
Methods, systems, and articles of manufacture for implementing multiple-patterning-aware design rule check for electronic designs Mar 14, 2013 Issued
Array ( [id] => 9548722 [patent_doc_number] => 20140173370 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-19 [patent_title] => 'DEBUG SYSTEM, APPARATUS AND METHOD THEREOF FOR PROVIDING GRAPHICAL PIN INTERFACE' [patent_app_type] => utility [patent_app_number] => 13/842154 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3002 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13842154 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/842154
Debug system, apparatus and method thereof for providing graphical pin interface Mar 14, 2013 Issued
Array ( [id] => 9853151 [patent_doc_number] => 08954898 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-10 [patent_title] => 'Source-mask optimization for a lithography process' [patent_app_type] => utility [patent_app_number] => 13/836327 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 10887 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13836327 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/836327
Source-mask optimization for a lithography process Mar 14, 2013 Issued
Array ( [id] => 9486667 [patent_doc_number] => 08732630 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-05-20 [patent_title] => 'Methods, systems, and articles of manufacture for implementing analog behavioral modeling and IP integration using systemverilog hardware description language' [patent_app_type] => utility [patent_app_number] => 13/831958 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 26 [patent_no_of_words] => 15087 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13831958 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/831958
Methods, systems, and articles of manufacture for implementing analog behavioral modeling and IP integration using systemverilog hardware description language Mar 14, 2013 Issued
Array ( [id] => 9746609 [patent_doc_number] => 20140282328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'DESIGN RULE CHECKS IN 3-D VIRTUAL FABRICATION ENVIRONMENT' [patent_app_type] => utility [patent_app_number] => 13/831444 [patent_app_country] => US [patent_app_date] => 2013-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 13820 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13831444 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/831444
Rule checks in 3-D virtual fabrication environment Mar 13, 2013 Issued
Array ( [id] => 9486675 [patent_doc_number] => 08732638 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-05-20 [patent_title] => 'Verifying proper representation of semiconductor device fingers' [patent_app_type] => utility [patent_app_number] => 13/799398 [patent_app_country] => US [patent_app_date] => 2013-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4772 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13799398 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/799398
Verifying proper representation of semiconductor device fingers Mar 12, 2013 Issued
Array ( [id] => 9623445 [patent_doc_number] => 08793640 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-07-29 [patent_title] => 'Methods and apparatus for RC extraction' [patent_app_type] => utility [patent_app_number] => 13/795814 [patent_app_country] => US [patent_app_date] => 2013-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 8683 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13795814 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/795814
Methods and apparatus for RC extraction Mar 11, 2013 Issued
Array ( [id] => 9527694 [patent_doc_number] => 08751985 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-06-10 [patent_title] => 'Hierarchical layout versus schematic (LVS) comparison with extraneous device elimination' [patent_app_type] => utility [patent_app_number] => 13/795198 [patent_app_country] => US [patent_app_date] => 2013-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 6763 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13795198 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/795198
Hierarchical layout versus schematic (LVS) comparison with extraneous device elimination Mar 11, 2013 Issued
Array ( [id] => 9555836 [patent_doc_number] => 08762909 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-06-24 [patent_title] => 'System and method for automatic timing-based register placement and register location adjustment in an integrated circuit (IC)' [patent_app_type] => utility [patent_app_number] => 13/796078 [patent_app_country] => US [patent_app_date] => 2013-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 4526 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13796078 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/796078
System and method for automatic timing-based register placement and register location adjustment in an integrated circuit (IC) Mar 11, 2013 Issued
Array ( [id] => 9431143 [patent_doc_number] => 08707230 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-04-22 [patent_title] => 'Method and system for semiconductor simulation' [patent_app_type] => utility [patent_app_number] => 13/792827 [patent_app_country] => US [patent_app_date] => 2013-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6400 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13792827 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/792827
Method and system for semiconductor simulation Mar 10, 2013 Issued
Array ( [id] => 9723249 [patent_doc_number] => 20140258951 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-11 [patent_title] => 'Prioritized Design for Manufacturing Virtualization with Design Rule Checking Filtering' [patent_app_type] => utility [patent_app_number] => 13/788046 [patent_app_country] => US [patent_app_date] => 2013-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4371 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13788046 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/788046
Prioritized design for manufacturing virtualization with design rule checking filtering Mar 6, 2013 Issued
Array ( [id] => 9810208 [patent_doc_number] => 20150022153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-22 [patent_title] => 'DETECTION OF A LEAKAGE CURRENT COMPRISING A CONTINUOUS COMPONENT IN A VEHICLE' [patent_app_type] => utility [patent_app_number] => 14/380942 [patent_app_country] => US [patent_app_date] => 2013-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10952 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14380942 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/380942
Detection of a leakage current comprising a continuous component in a vehicle Feb 27, 2013 Issued
Array ( [id] => 9328303 [patent_doc_number] => 20140055085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-27 [patent_title] => 'THIN FILM BATTERY CHARGE CONTROL AND METHOD' [patent_app_type] => utility [patent_app_number] => 14/003711 [patent_app_country] => US [patent_app_date] => 2013-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3090 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14003711 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/003711
THIN FILM BATTERY CHARGE CONTROL AND METHOD Feb 21, 2013 Abandoned
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