
Suchin Parihar
Examiner (ID: 4481)
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2825, 2851, 2872 |
| Total Applications | 1385 |
| Issued Applications | 1167 |
| Pending Applications | 109 |
| Abandoned Applications | 148 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 9458717
[patent_doc_number] => 08719744
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-05-06
[patent_title] => 'Language conversion method and language conversion program'
[patent_app_type] => utility
[patent_app_number] => 13/492077
[patent_app_country] => US
[patent_app_date] => 2012-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 24
[patent_no_of_words] => 10333
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13492077
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/492077 | Language conversion method and language conversion program | Jun 7, 2012 | Issued |
Array
(
[id] => 8518116
[patent_doc_number] => 20120317524
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-12-13
[patent_title] => 'MASK DATA VERIFICATION APPARATUS, DESIGN LAYOUT VERIFICATION APPARATUS, METHOD THEREOF, AND COMPUTER PROGRAM THEREOF'
[patent_app_type] => utility
[patent_app_number] => 13/491082
[patent_app_country] => US
[patent_app_date] => 2012-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 32
[patent_no_of_words] => 15103
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13491082
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/491082 | Mask data verification apparatus, design layout verification apparatus, method thereof, and computer program thereof | Jun 6, 2012 | Issued |
Array
(
[id] => 10873389
[patent_doc_number] => 08898610
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-11-25
[patent_title] => 'Creating cell libraries with a large number of cells'
[patent_app_type] => utility
[patent_app_number] => 13/487612
[patent_app_country] => US
[patent_app_date] => 2012-06-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 39
[patent_no_of_words] => 10764
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 12
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13487612
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/487612 | Creating cell libraries with a large number of cells | Jun 3, 2012 | Issued |
| 13/487062 | Structured Latch and Local-Clock-Buffer Planning | May 31, 2012 | Abandoned |
Array
(
[id] => 8722806
[patent_doc_number] => 20130074023
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-03-21
[patent_title] => 'Test Functionality Integrity Verification for Integrated Circuit Design'
[patent_app_type] => utility
[patent_app_number] => 13/484222
[patent_app_country] => US
[patent_app_date] => 2012-05-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5006
[patent_no_of_claims] => 44
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13484222
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/484222 | Test functionality integrity verification for integrated circuit design | May 29, 2012 | Issued |
Array
(
[id] => 9404862
[patent_doc_number] => 08694926
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-04-08
[patent_title] => 'Techniques for checking computer-aided design layers of a device to reduce the occurrence of missing deck rules'
[patent_app_type] => utility
[patent_app_number] => 13/484022
[patent_app_country] => US
[patent_app_date] => 2012-05-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 3906
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13484022
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/484022 | Techniques for checking computer-aided design layers of a device to reduce the occurrence of missing deck rules | May 29, 2012 | Issued |
Array
(
[id] => 8504728
[patent_doc_number] => 20120304136
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-11-29
[patent_title] => 'Clock Tree Planning for an ASIC'
[patent_app_type] => utility
[patent_app_number] => 13/478272
[patent_app_country] => US
[patent_app_date] => 2012-05-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5342
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13478272
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/478272 | Clock tree planning for an ASIC | May 22, 2012 | Issued |
Array
(
[id] => 8619511
[patent_doc_number] => 20130024823
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-01-24
[patent_title] => 'METHOD AND APPARATUS FOR DESIGNING PATTERNING SYSTEM BASED ON PATTERNING FIDELITY'
[patent_app_type] => utility
[patent_app_number] => 13/478131
[patent_app_country] => US
[patent_app_date] => 2012-05-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3100
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13478131
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/478131 | Method and apparatus for designing patterning system based on patterning fidelity | May 22, 2012 | Issued |
Array
(
[id] => 8861639
[patent_doc_number] => 08464193
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2013-06-11
[patent_title] => 'Optical proximity correction (OPC) methodology employing multiple OPC programs'
[patent_app_type] => utility
[patent_app_number] => 13/474752
[patent_app_country] => US
[patent_app_date] => 2012-05-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 42
[patent_no_of_words] => 11465
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 261
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13474752
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/474752 | Optical proximity correction (OPC) methodology employing multiple OPC programs | May 17, 2012 | Issued |
Array
(
[id] => 8669360
[patent_doc_number] => 20130043898
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-02-21
[patent_title] => 'SYSTEM WITH A DEFECT TOLERANT CONFIGURABLE IC'
[patent_app_type] => utility
[patent_app_number] => 13/474681
[patent_app_country] => US
[patent_app_date] => 2012-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 26
[patent_no_of_words] => 10297
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13474681
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/474681 | SYSTEM WITH A DEFECT TOLERANT CONFIGURABLE IC | May 16, 2012 | Abandoned |
Array
(
[id] => 9077632
[patent_doc_number] => 08555224
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-10-08
[patent_title] => 'Circuit simulation method and semiconductor integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 13/471061
[patent_app_country] => US
[patent_app_date] => 2012-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 6587
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13471061
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/471061 | Circuit simulation method and semiconductor integrated circuit | May 13, 2012 | Issued |
Array
(
[id] => 8655573
[patent_doc_number] => 08375341
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-02-12
[patent_title] => 'Method for improving the radio frequency linearity of silicon-on-insulator MOSFET circuits'
[patent_app_type] => utility
[patent_app_number] => 13/470292
[patent_app_country] => US
[patent_app_date] => 2012-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4249
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 200
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13470292
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/470292 | Method for improving the radio frequency linearity of silicon-on-insulator MOSFET circuits | May 11, 2012 | Issued |
Array
(
[id] => 8849423
[patent_doc_number] => 08458623
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2013-06-04
[patent_title] => 'Mitigation of mask defects by pattern shifting'
[patent_app_type] => utility
[patent_app_number] => 13/467191
[patent_app_country] => US
[patent_app_date] => 2012-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 33
[patent_no_of_words] => 17352
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 178
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13467191
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/467191 | Mitigation of mask defects by pattern shifting | May 8, 2012 | Issued |
Array
(
[id] => 9781481
[patent_doc_number] => 08856705
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-10-07
[patent_title] => 'Mismatch verification device and methods thereof'
[patent_app_type] => utility
[patent_app_number] => 13/466642
[patent_app_country] => US
[patent_app_date] => 2012-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 15
[patent_no_of_words] => 9783
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13466642
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/466642 | Mismatch verification device and methods thereof | May 7, 2012 | Issued |
Array
(
[id] => 9367891
[patent_doc_number] => 20140077764
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-03-20
[patent_title] => 'Method for Battery Management and Diagnosis'
[patent_app_type] => utility
[patent_app_number] => 14/115951
[patent_app_country] => US
[patent_app_date] => 2012-05-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2386
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14115951
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/115951 | Method for battery management and diagnosis | May 6, 2012 | Issued |
Array
(
[id] => 9824174
[patent_doc_number] => 08933661
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-01-13
[patent_title] => 'Integrated inductive and conductive electrical charging system'
[patent_app_type] => utility
[patent_app_number] => 13/460202
[patent_app_country] => US
[patent_app_date] => 2012-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4427
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13460202
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/460202 | Integrated inductive and conductive electrical charging system | Apr 29, 2012 | Issued |
Array
(
[id] => 9105088
[patent_doc_number] => 20130278219
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-10-24
[patent_title] => 'Battery Testing System and Control Method for Battery Testing System'
[patent_app_type] => utility
[patent_app_number] => 13/460715
[patent_app_country] => US
[patent_app_date] => 2012-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3909
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13460715
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/460715 | Battery Testing System and Control Method for Battery Testing System | Apr 29, 2012 | Abandoned |
Array
(
[id] => 11266341
[patent_doc_number] => 09490648
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-11-08
[patent_title] => 'Alternating current direct current adapter with wireless charging'
[patent_app_type] => utility
[patent_app_number] => 13/460138
[patent_app_country] => US
[patent_app_date] => 2012-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5422
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13460138
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/460138 | Alternating current direct current adapter with wireless charging | Apr 29, 2012 | Issued |
Array
(
[id] => 9187250
[patent_doc_number] => 08627251
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-01-07
[patent_title] => 'Systems and methods of automatically detecting failure patterns for semiconductor wafer fabrication processes'
[patent_app_type] => utility
[patent_app_number] => 13/455186
[patent_app_country] => US
[patent_app_date] => 2012-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 19
[patent_no_of_words] => 10764
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 252
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13455186
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/455186 | Systems and methods of automatically detecting failure patterns for semiconductor wafer fabrication processes | Apr 24, 2012 | Issued |
Array
(
[id] => 9110093
[patent_doc_number] => 20130283225
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-10-24
[patent_title] => 'DATAPATH PLACEMENT USING TIERED ASSIGNMENT'
[patent_app_type] => utility
[patent_app_number] => 13/451382
[patent_app_country] => US
[patent_app_date] => 2012-04-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6623
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13451382
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/451382 | Datapath placement using tiered assignment | Apr 18, 2012 | Issued |