
Suchin Parihar
Examiner (ID: 4041, Phone: (571)272-6210 , Office: P/2851 )
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2825, 2851, 2872 |
| Total Applications | 1418 |
| Issued Applications | 1198 |
| Pending Applications | 84 |
| Abandoned Applications | 154 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 9029813
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[patent_title] => 'Semiconductor device, adjustment method thereof and data processing system'
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Array
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[patent_issue_date] => 2016-02-23
[patent_title] => 'Designing photonic switching systems utilizing equalized drivers'
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Array
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[patent_title] => 'METHOD OF ANALYZING INTERCONNECT FOR GLOBAL CIRCUIT WIRES'
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Array
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[patent_title] => 'Integrated circuit characterization based on measured and static apparent resistances'
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/603402 | Automatic verification of dependency | Sep 3, 2012 | Issued |
Array
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Array
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[patent_title] => 'System and method for automatic placement of contact cuts and similar structures in integrated circuit layouts'
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Array
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[id] => 8504736
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[patent_title] => 'Power Mesh Managing Method'
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Array
(
[id] => 9199493
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[patent_title] => 'Method and Apparatus for Hierarchical Wafer Quality Predictive Modeling'
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Array
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[id] => 8611015
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Array
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Array
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Array
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Array
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| 13/487062 | Structured Latch and Local-Clock-Buffer Planning | May 31, 2012 | Abandoned |
Array
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Array
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Array
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