Search

Suchin Parihar

Examiner (ID: 4481, Phone: (571)272-6210 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851, 2872
Total Applications
1385
Issued Applications
1167
Pending Applications
109
Abandoned Applications
148

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9367396 [patent_doc_number] => 20140077269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-20 [patent_title] => 'COMPACT REGULAR RECONFIGURABLE FABRICS' [patent_app_type] => utility [patent_app_number] => 13/883189 [patent_app_country] => US [patent_app_date] => 2011-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5158 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13883189 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/883189
COMPACT REGULAR RECONFIGURABLE FABRICS Nov 1, 2011 Abandoned
Array ( [id] => 9486677 [patent_doc_number] => 08732640 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-05-20 [patent_title] => 'Methods, systems, and articles for multi-scenario physically-aware design methodology for layout-dependent effects' [patent_app_type] => utility [patent_app_number] => 13/282362 [patent_app_country] => US [patent_app_date] => 2011-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12858 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13282362 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/282362
Methods, systems, and articles for multi-scenario physically-aware design methodology for layout-dependent effects Oct 25, 2011 Issued
Array ( [id] => 8169414 [patent_doc_number] => 20120106229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/317167 [patent_app_country] => US [patent_app_date] => 2011-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8687 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20120106229.pdf [firstpage_image] =>[orig_patent_app_number] => 13317167 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/317167
Semiconductor device Oct 11, 2011 Abandoned
Array ( [id] => 8959165 [patent_doc_number] => 08504958 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-06 [patent_title] => 'Method and apparatus for thermal analysis' [patent_app_type] => utility [patent_app_number] => 13/269550 [patent_app_country] => US [patent_app_date] => 2011-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 11914 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13269550 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/269550
Method and apparatus for thermal analysis Oct 6, 2011 Issued
Array ( [id] => 8667682 [patent_doc_number] => 08381155 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-02-19 [patent_title] => 'Vertical interconnect patterns in multi-layer integrated circuits' [patent_app_type] => utility [patent_app_number] => 13/200831 [patent_app_country] => US [patent_app_date] => 2011-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 9348 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13200831 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/200831
Vertical interconnect patterns in multi-layer integrated circuits Oct 2, 2011 Issued
Array ( [id] => 8240206 [patent_doc_number] => 20120148943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-14 [patent_title] => 'Method for Determining A Grey Level Etch Mask' [patent_app_type] => utility [patent_app_number] => 13/241011 [patent_app_country] => US [patent_app_date] => 2011-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3641 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13241011 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/241011
Method for determining a grey level etch mask Sep 21, 2011 Issued
Array ( [id] => 8667683 [patent_doc_number] => 08381156 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-02-19 [patent_title] => '3D inter-stratum connectivity robustness' [patent_app_type] => utility [patent_app_number] => 13/217381 [patent_app_country] => US [patent_app_date] => 2011-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 5599 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13217381 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/217381
3D inter-stratum connectivity robustness Aug 24, 2011 Issued
Array ( [id] => 8672589 [patent_doc_number] => 20130047127 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-21 [patent_title] => 'METHOD AND APPARATUS FOR AUTOMATIC RELATIVE PLACEMENT GENERATION FOR CLOCK TREES' [patent_app_type] => utility [patent_app_number] => 13/212061 [patent_app_country] => US [patent_app_date] => 2011-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 13282 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13212061 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/212061
Method and apparatus for automatic relative placement generation for clock trees Aug 16, 2011 Issued
Array ( [id] => 7582478 [patent_doc_number] => 20110296361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-01 [patent_title] => 'CIRCUIT ANALYSIS METHOD' [patent_app_type] => utility [patent_app_number] => 13/209071 [patent_app_country] => US [patent_app_date] => 2011-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9917 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20110296361.pdf [firstpage_image] =>[orig_patent_app_number] => 13209071 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/209071
CIRCUIT ANALYSIS METHOD Aug 11, 2011 Abandoned
Array ( [id] => 8661381 [patent_doc_number] => 20130042210 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-14 [patent_title] => 'CYCLE TIME REDUCTION IN DATA PREPARATION' [patent_app_type] => utility [patent_app_number] => 13/207691 [patent_app_country] => US [patent_app_date] => 2011-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8133 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13207691 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/207691
Cycle time reduction in data preparation Aug 10, 2011 Issued
Array ( [id] => 7569402 [patent_doc_number] => 20110289465 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-24 [patent_title] => 'Statistical On-Chip Variation Timing Analysis' [patent_app_type] => utility [patent_app_number] => 13/195582 [patent_app_country] => US [patent_app_date] => 2011-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9758 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0289/20110289465.pdf [firstpage_image] =>[orig_patent_app_number] => 13195582 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/195582
Statistical on-chip variation timing analysis Jul 31, 2011 Issued
Array ( [id] => 8837318 [patent_doc_number] => 08453087 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-28 [patent_title] => 'Method and apparatus for preemptive design verification via partial pattern matching' [patent_app_type] => utility [patent_app_number] => 13/193961 [patent_app_country] => US [patent_app_date] => 2011-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10597 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13193961 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/193961
Method and apparatus for preemptive design verification via partial pattern matching Jul 28, 2011 Issued
Array ( [id] => 9169967 [patent_doc_number] => 08595661 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-26 [patent_title] => 'N-channel and p-channel finFET cell architecture' [patent_app_type] => utility [patent_app_number] => 13/194862 [patent_app_country] => US [patent_app_date] => 2011-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 11692 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13194862 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/194862
N-channel and p-channel finFET cell architecture Jul 28, 2011 Issued
Array ( [id] => 8581027 [patent_doc_number] => 08347259 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-01-01 [patent_title] => 'Circuit enhancement by multiplicate-layer-handling circuit simulation' [patent_app_type] => utility [patent_app_number] => 13/193721 [patent_app_country] => US [patent_app_date] => 2011-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7495 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13193721 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/193721
Circuit enhancement by multiplicate-layer-handling circuit simulation Jul 28, 2011 Issued
Array ( [id] => 11802712 [patent_doc_number] => 09543622 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-10 [patent_title] => 'Lithium solid state secondary battery system' [patent_app_type] => utility [patent_app_number] => 14/234567 [patent_app_country] => US [patent_app_date] => 2011-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 11999 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14234567 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/234567
Lithium solid state secondary battery system Jul 25, 2011 Issued
Array ( [id] => 8787193 [patent_doc_number] => 08434048 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-30 [patent_title] => 'Method for implementing power gating in an integrated circuit design logic block including N-nary dynamic logic (NDL) gates' [patent_app_type] => utility [patent_app_number] => 13/178892 [patent_app_country] => US [patent_app_date] => 2011-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5589 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13178892 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/178892
Method for implementing power gating in an integrated circuit design logic block including N-nary dynamic logic (NDL) gates Jul 7, 2011 Issued
Array ( [id] => 9302276 [patent_doc_number] => 08650520 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-11 [patent_title] => 'Integrated circuit module and manufacturing methods and application thereof' [patent_app_type] => utility [patent_app_number] => 13/174832 [patent_app_country] => US [patent_app_date] => 2011-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4328 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13174832 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/174832
Integrated circuit module and manufacturing methods and application thereof Jun 30, 2011 Issued
Array ( [id] => 9302269 [patent_doc_number] => 08650513 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-11 [patent_title] => 'Reducing x-pessimism in gate-level simulation and verification' [patent_app_type] => utility [patent_app_number] => 13/174531 [patent_app_country] => US [patent_app_date] => 2011-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 6931 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13174531 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/174531
Reducing x-pessimism in gate-level simulation and verification Jun 29, 2011 Issued
Array ( [id] => 9348291 [patent_doc_number] => 08667454 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-03-04 [patent_title] => 'System, method, and computer program product for optimizing pins' [patent_app_type] => utility [patent_app_number] => 13/160992 [patent_app_country] => US [patent_app_date] => 2011-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 8236 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13160992 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/160992
System, method, and computer program product for optimizing pins Jun 14, 2011 Issued
Array ( [id] => 8518122 [patent_doc_number] => 20120317530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-13 [patent_title] => 'SOLUTIONS FOR ON-CHIP MODELING OF OPEN TERMINATION OF FRINGE CAPACITANCE' [patent_app_type] => utility [patent_app_number] => 13/158562 [patent_app_country] => US [patent_app_date] => 2011-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4172 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13158562 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/158562
Solutions for on-chip modeling of open termination of fringe capacitance Jun 12, 2011 Issued
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