Suchin Parihar

Array ( [id] => 8935817 [patent_doc_number] => 08495539 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-07-23 [patent_title] => 'Scheduling processes in simulation of a circuit design' [patent_app_type] => utility [patent_app_number] => 13/347301 [patent_app_country] => US [patent_app_date] => 2012-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3579 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13347301 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8176982 [patent_doc_number] => 20120110539 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'Automatically Routing Nets with Variable Spacing' [patent_app_type] => utility [patent_app_number] => 13/346491 [patent_app_country] => US [patent_app_date] => 2012-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 14463 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20120110539.pdf [firstpage_image] =>[orig_patent_app_number] => 13346491 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8878904 [patent_doc_number] => 08473889 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-25 [patent_title] => 'Routing storage structure based on directional grid points and routing method thereof' [patent_app_type] => utility [patent_app_number] => 13/342102 [patent_app_country] => US [patent_app_date] => 2012-01-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4519 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13342102 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8333260 [patent_doc_number] => 20120199973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-09 [patent_title] => 'INTERCHANGEABLE CONNECTION ARRAYS FOR DOUBLE-SIDED DIMM PLACEMENT' [patent_app_type] => utility [patent_app_number] => 13/339525 [patent_app_country] => US [patent_app_date] => 2011-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2679 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13339525 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9118693 [patent_doc_number] => 20130285615 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-31 [patent_title] => 'MODULE FOR CONVERTING VOLTAGE BETWEEN A HIGH-VOLTAGE ELECTRICAL NETWORK OF AN AIRCRAFT AND AN ENERGY STORAGE ELEMENT' [patent_app_type] => utility [patent_app_number] => 13/976215 [patent_app_country] => US [patent_app_date] => 2011-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6311 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13976215 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8893912 [patent_doc_number] => 20130167096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-27 [patent_title] => 'LOCATION AND TIMING WINDOW BASED DECOUPLING CAPACITOR EVAULATION TOOL AND METHOD' [patent_app_type] => utility [patent_app_number] => 13/334542 [patent_app_country] => US [patent_app_date] => 2011-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6031 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13334542 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8372592 [patent_doc_number] => 20120221989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-30 [patent_title] => 'ELECTRONIC DEVICE AND METHOD OF AUTOMATICALLY TESTING TRANSMISSION LINES' [patent_app_type] => utility [patent_app_number] => 13/326652 [patent_app_country] => US [patent_app_date] => 2011-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1532 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13326652 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8912527 [patent_doc_number] => 08484604 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-09 [patent_title] => 'Constructing a clock tree for an integrated circuit design' [patent_app_type] => utility [patent_app_number] => 13/325102 [patent_app_country] => US [patent_app_date] => 2011-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6954 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13325102 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8855658 [patent_doc_number] => 20130145333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-06 [patent_title] => 'STATISTICAL CLOCK CYCLE COMPUTATION' [patent_app_type] => utility [patent_app_number] => 13/311832 [patent_app_country] => US [patent_app_date] => 2011-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7749 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13311832 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9105081 [patent_doc_number] => 20130278212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-24 [patent_title] => 'NON-CONTACT CHARGING DEVICE' [patent_app_type] => utility [patent_app_number] => 13/976169 [patent_app_country] => US [patent_app_date] => 2011-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 16694 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13976169 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9049394 [patent_doc_number] => 08543952 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-24 [patent_title] => 'Method and apparatus for thermal analysis of through-silicon via (TSV)' [patent_app_type] => utility [patent_app_number] => 13/290047 [patent_app_country] => US [patent_app_date] => 2011-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 48 [patent_no_of_words] => 17931 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13290047 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9316882 [patent_doc_number] => 20140049220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-20 [patent_title] => 'Alternating Current Digital Universal Charger' [patent_app_type] => utility [patent_app_number] => 13/979590 [patent_app_country] => US [patent_app_date] => 2011-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2720 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13979590 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8219420 [patent_doc_number] => 20120134193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-31 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING PLURAL MEMORY CHIP' [patent_app_type] => utility [patent_app_number] => 13/288631 [patent_app_country] => US [patent_app_date] => 2011-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6579 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13288631 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9367396 [patent_doc_number] => 20140077269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-20 [patent_title] => 'COMPACT REGULAR RECONFIGURABLE FABRICS' [patent_app_type] => utility [patent_app_number] => 13/883189 [patent_app_country] => US [patent_app_date] => 2011-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5158 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13883189 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9486677 [patent_doc_number] => 08732640 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-05-20 [patent_title] => 'Methods, systems, and articles for multi-scenario physically-aware design methodology for layout-dependent effects' [patent_app_type] => utility [patent_app_number] => 13/282362 [patent_app_country] => US [patent_app_date] => 2011-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12858 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13282362 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8169414 [patent_doc_number] => 20120106229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/317167 [patent_app_country] => US [patent_app_date] => 2011-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8687 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20120106229.pdf [firstpage_image] =>[orig_patent_app_number] => 13317167 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8959165 [patent_doc_number] => 08504958 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-06 [patent_title] => 'Method and apparatus for thermal analysis' [patent_app_type] => utility [patent_app_number] => 13/269550 [patent_app_country] => US [patent_app_date] => 2011-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 11914 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13269550 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8667682 [patent_doc_number] => 08381155 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-02-19 [patent_title] => 'Vertical interconnect patterns in multi-layer integrated circuits' [patent_app_type] => utility [patent_app_number] => 13/200831 [patent_app_country] => US [patent_app_date] => 2011-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 9348 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13200831 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8240206 [patent_doc_number] => 20120148943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-14 [patent_title] => 'Method for Determining A Grey Level Etch Mask' [patent_app_type] => utility [patent_app_number] => 13/241011 [patent_app_country] => US [patent_app_date] => 2011-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3641 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13241011 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8667683 [patent_doc_number] => 08381156 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-02-19 [patent_title] => '3D inter-stratum connectivity robustness' [patent_app_type] => utility [patent_app_number] => 13/217381 [patent_app_country] => US [patent_app_date] => 2011-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 5599 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13217381 [rel_patent_id] =>[rel_patent_doc_number] =>)