Search

Suchin Parihar

Examiner (ID: 4481, Phone: (571)272-6210 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851, 2872
Total Applications
1385
Issued Applications
1167
Pending Applications
109
Abandoned Applications
148

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10873393 [patent_doc_number] => 08898611 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-25 [patent_title] => 'VLSI layouts of fully connected generalized and pyramid networks with locality exploitation' [patent_app_type] => utility [patent_app_number] => 13/502207 [patent_app_country] => US [patent_app_date] => 2010-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 51 [patent_no_of_words] => 47603 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 518 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13502207 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/502207
VLSI layouts of fully connected generalized and pyramid networks with locality exploitation Oct 15, 2010 Issued
Array ( [id] => 6121693 [patent_doc_number] => 20110084744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-14 [patent_title] => 'Semiconductor device, adjustment method thereof and data processing system' [patent_app_type] => utility [patent_app_number] => 12/923792 [patent_app_country] => US [patent_app_date] => 2010-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 17848 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20110084744.pdf [firstpage_image] =>[orig_patent_app_number] => 12923792 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/923792
Semiconductor device, adjustment method thereof and data processing system Oct 6, 2010 Issued
Array ( [id] => 8096919 [patent_doc_number] => 20120084067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-05 [patent_title] => 'METHOD AND APPARATUS FOR SYNTHESIZING PIPELINED INPUT/OUTPUT IN A CIRCUIT DESIGN FROM HIGH LEVEL SYNTHESIS' [patent_app_type] => utility [patent_app_number] => 12/894902 [patent_app_country] => US [patent_app_date] => 2010-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12717 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20120084067.pdf [firstpage_image] =>[orig_patent_app_number] => 12894902 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/894902
Method and apparatus for synthesizing pipelined input/output in a circuit design from high level synthesis Sep 29, 2010 Issued
Array ( [id] => 8098271 [patent_doc_number] => 20120084742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-05 [patent_title] => 'METHOD AND APPARATUS FOR USING ENTROPY IN ANT COLONY OPTIMIZATION CIRCUIT DESIGN FROM HIGH LEVEL SYNTHESIS' [patent_app_type] => utility [patent_app_number] => 12/894756 [patent_app_country] => US [patent_app_date] => 2010-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12672 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20120084742.pdf [firstpage_image] =>[orig_patent_app_number] => 12894756 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/894756
Method and apparatus for using entropy in ant colony optimization circuit design from high level synthesis Sep 29, 2010 Issued
Array ( [id] => 8098275 [patent_doc_number] => 20120084743 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-05 [patent_title] => 'METHOD AND APPARATUS FOR IMPROVING THE INTERCONNECTION AND MULTIPLEXING COST OF CIRCUIT DESIGN FROM HIGH LEVEL SYNTHESIS USING ANT COLONY OPTIMIZATION' [patent_app_type] => utility [patent_app_number] => 12/894842 [patent_app_country] => US [patent_app_date] => 2010-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12698 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20120084743.pdf [firstpage_image] =>[orig_patent_app_number] => 12894842 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/894842
Method and apparatus for improving the interconnection and multiplexing cost of circuit design from high level synthesis using ant colony optimization Sep 29, 2010 Issued
Array ( [id] => 8985293 [patent_doc_number] => 08516423 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-20 [patent_title] => 'System and method for determining simulated response extrema for integrated circuit power supply networks' [patent_app_type] => utility [patent_app_number] => 12/894102 [patent_app_country] => US [patent_app_date] => 2010-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 16741 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12894102 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/894102
System and method for determining simulated response extrema for integrated circuit power supply networks Sep 28, 2010 Issued
Array ( [id] => 6146705 [patent_doc_number] => 20110018879 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-27 [patent_title] => 'Pattern generation method and pattern generation program' [patent_app_type] => utility [patent_app_number] => 12/923512 [patent_app_country] => US [patent_app_date] => 2010-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5148 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20110018879.pdf [firstpage_image] =>[orig_patent_app_number] => 12923512 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/923512
Pattern generation method and pattern generation program Sep 23, 2010 Issued
Array ( [id] => 7493398 [patent_doc_number] => 20110239182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-29 [patent_title] => 'AUTOMATIC CIRCUIT DESIGN TECHNIQUE' [patent_app_type] => utility [patent_app_number] => 12/888700 [patent_app_country] => US [patent_app_date] => 2010-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 18692 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0239/20110239182.pdf [firstpage_image] =>[orig_patent_app_number] => 12888700 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/888700
Automatic circuit design technique using pareto optimal solutions Sep 22, 2010 Issued
Array ( [id] => 9276119 [patent_doc_number] => 08640067 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-01-28 [patent_title] => 'Method and apparatus for implementing a field programmable gate array clock skew' [patent_app_type] => utility [patent_app_number] => 12/807960 [patent_app_country] => US [patent_app_date] => 2010-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6082 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12807960 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/807960
Method and apparatus for implementing a field programmable gate array clock skew Sep 16, 2010 Issued
Array ( [id] => 8667680 [patent_doc_number] => 08381153 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-19 [patent_title] => 'Dissection splitting with optical proximity correction and mask rule check enforcement' [patent_app_type] => utility [patent_app_number] => 12/884442 [patent_app_country] => US [patent_app_date] => 2010-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 5644 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12884442 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/884442
Dissection splitting with optical proximity correction and mask rule check enforcement Sep 16, 2010 Issued
Array ( [id] => 6147635 [patent_doc_number] => 20110131541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-02 [patent_title] => 'SPICE CORNER MODEL GENERATING METHOD AND APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/881020 [patent_app_country] => US [patent_app_date] => 2010-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7666 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20110131541.pdf [firstpage_image] =>[orig_patent_app_number] => 12881020 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/881020
Spice corner model generating method and apparatus Sep 12, 2010 Issued
Array ( [id] => 8878901 [patent_doc_number] => 08473886 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-25 [patent_title] => 'Parallel parasitic processing in static timing analysis' [patent_app_type] => utility [patent_app_number] => 12/879682 [patent_app_country] => US [patent_app_date] => 2010-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4901 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12879682 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/879682
Parallel parasitic processing in static timing analysis Sep 9, 2010 Issued
Array ( [id] => 7793145 [patent_doc_number] => 20120054701 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-01 [patent_title] => 'Optimal Correlated Array Abstraction' [patent_app_type] => utility [patent_app_number] => 12/871962 [patent_app_country] => US [patent_app_date] => 2010-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12298 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20120054701.pdf [firstpage_image] =>[orig_patent_app_number] => 12871962 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/871962
Optimal correlated array abstraction Aug 30, 2010 Issued
Array ( [id] => 8752262 [patent_doc_number] => 08418106 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-09 [patent_title] => 'Techniques for employing retiming and transient simplification on netlists that include memory arrays' [patent_app_type] => utility [patent_app_number] => 12/872490 [patent_app_country] => US [patent_app_date] => 2010-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7445 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12872490 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/872490
Techniques for employing retiming and transient simplification on netlists that include memory arrays Aug 30, 2010 Issued
Array ( [id] => 7780737 [patent_doc_number] => 20120042293 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-16 [patent_title] => 'SYNCHRONIZING TAP CONTROLLER AFTER POWER IS RESTORED' [patent_app_type] => utility [patent_app_number] => 12/853940 [patent_app_country] => US [patent_app_date] => 2010-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2414 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20120042293.pdf [firstpage_image] =>[orig_patent_app_number] => 12853940 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/853940
Synchronizing TAP controller after power is restored Aug 9, 2010 Issued
Array ( [id] => 8678846 [patent_doc_number] => 08386983 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-02-26 [patent_title] => 'Parallel signal routing' [patent_app_type] => utility [patent_app_number] => 12/853810 [patent_app_country] => US [patent_app_date] => 2010-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7911 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 308 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12853810 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/853810
Parallel signal routing Aug 9, 2010 Issued
Array ( [id] => 6032184 [patent_doc_number] => 20110055795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'Design Support Apparatus and Design Support Method' [patent_app_type] => utility [patent_app_number] => 12/845410 [patent_app_country] => US [patent_app_date] => 2010-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7113 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20110055795.pdf [firstpage_image] =>[orig_patent_app_number] => 12845410 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/845410
Support apparatus and design support method Jul 27, 2010 Issued
Array ( [id] => 5933074 [patent_doc_number] => 20110041113 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-17 [patent_title] => 'DESIGN SUPPORT PROGRAM, DESIGN SUPPORT SYSTEM, AND DESIGN SUPPORT METHOD' [patent_app_type] => utility [patent_app_number] => 12/842710 [patent_app_country] => US [patent_app_date] => 2010-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6132 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20110041113.pdf [firstpage_image] =>[orig_patent_app_number] => 12842710 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/842710
Support program, design support system, and design support method Jul 22, 2010 Issued
Array ( [id] => 8401524 [patent_doc_number] => 08271919 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-18 [patent_title] => 'Method for correcting image rendering data, method for rendering image, method for manufacturing wiring board, and image rendering system' [patent_app_type] => utility [patent_app_number] => 12/841200 [patent_app_country] => US [patent_app_date] => 2010-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 4737 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12841200 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/841200
Method for correcting image rendering data, method for rendering image, method for manufacturing wiring board, and image rendering system Jul 21, 2010 Issued
Array ( [id] => 7582475 [patent_doc_number] => 20110296358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-01 [patent_title] => 'Computing Resistance Sensitivities with Respect to Geometric Parameters of Conductors with Arbitrary Shapes' [patent_app_type] => utility [patent_app_number] => 12/786572 [patent_app_country] => US [patent_app_date] => 2010-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8422 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20110296358.pdf [firstpage_image] =>[orig_patent_app_number] => 12786572 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/786572
Computing resistance sensitivities with respect to geometric parameters of conductors with arbitrary shapes May 24, 2010 Issued
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