
Suchin Parihar
Examiner (ID: 4041, Phone: (571)272-6210 , Office: P/2851 )
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2825, 2851, 2872 |
| Total Applications | 1418 |
| Issued Applications | 1198 |
| Pending Applications | 84 |
| Abandoned Applications | 154 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8655570
[patent_doc_number] => 08375338
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2013-02-12
[patent_title] => 'Estimating the rate of storage corruption from atomic particles'
[patent_app_type] => utility
[patent_app_number] => 12/975102
[patent_app_country] => US
[patent_app_date] => 2010-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5129
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12975102
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/975102 | Estimating the rate of storage corruption from atomic particles | Dec 20, 2010 | Issued |
Array
(
[id] => 9023644
[patent_doc_number] => 08533643
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-09-10
[patent_title] => 'Method and apparatus for performing template-based classification of a circuit design'
[patent_app_type] => utility
[patent_app_number] => 12/971442
[patent_app_country] => US
[patent_app_date] => 2010-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 2882
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12971442
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/971442 | Method and apparatus for performing template-based classification of a circuit design | Dec 16, 2010 | Issued |
Array
(
[id] => 9251936
[patent_doc_number] => 08615727
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-12-24
[patent_title] => 'Simultaneous multi-corner static timing analysis using samples-based static timing infrastructure'
[patent_app_type] => utility
[patent_app_number] => 12/970812
[patent_app_country] => US
[patent_app_date] => 2010-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 8182
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12970812
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/970812 | Simultaneous multi-corner static timing analysis using samples-based static timing infrastructure | Dec 15, 2010 | Issued |
Array
(
[id] => 8230152
[patent_doc_number] => 20120144357
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-06-07
[patent_title] => 'Method for Enabling Multiple Incompatible or Costly Timing Environments for Efficient Timing Closure'
[patent_app_type] => utility
[patent_app_number] => 12/958431
[patent_app_country] => US
[patent_app_date] => 2010-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3552
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12958431
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/958431 | Method for enabling multiple incompatible or costly timing environment for efficient timing closure | Dec 1, 2010 | Issued |
Array
(
[id] => 8087777
[patent_doc_number] => 08151219
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-04-03
[patent_title] => 'System and method for multi-exposure pattern decomposition'
[patent_app_type] => utility
[patent_app_number] => 12/955895
[patent_app_country] => US
[patent_app_date] => 2010-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 31
[patent_no_of_words] => 12346
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/151/08151219.pdf
[firstpage_image] =>[orig_patent_app_number] => 12955895
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/955895 | System and method for multi-exposure pattern decomposition | Nov 28, 2010 | Issued |
Array
(
[id] => 7726412
[patent_doc_number] => 08099692
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2012-01-17
[patent_title] => 'Power-driven timing analysis and placement for programmable logic'
[patent_app_type] => utility
[patent_app_number] => 12/953764
[patent_app_country] => US
[patent_app_date] => 2010-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 6184
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/099/08099692.pdf
[firstpage_image] =>[orig_patent_app_number] => 12953764
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/953764 | Power-driven timing analysis and placement for programmable logic | Nov 23, 2010 | Issued |
Array
(
[id] => 8552408
[patent_doc_number] => 08327307
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-12-04
[patent_title] => 'Method and system for eliminating implementation timing in synchronization circuits'
[patent_app_type] => utility
[patent_app_number] => 12/953022
[patent_app_country] => US
[patent_app_date] => 2010-11-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2994
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12953022
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/953022 | Method and system for eliminating implementation timing in synchronization circuits | Nov 22, 2010 | Issued |
Array
(
[id] => 8655572
[patent_doc_number] => 08375340
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-02-12
[patent_title] => 'Apparatus for manufacturing substrate for testing, method for manufacturing substrate for testing and recording medium'
[patent_app_type] => utility
[patent_app_number] => 12/952112
[patent_app_country] => US
[patent_app_date] => 2010-11-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6670
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 236
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12952112
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/952112 | Apparatus for manufacturing substrate for testing, method for manufacturing substrate for testing and recording medium | Nov 21, 2010 | Issued |
Array
(
[id] => 8678839
[patent_doc_number] => 08386976
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-02-26
[patent_title] => 'Method for producing layout of semiconductor integrated circuit with radio frequency devices'
[patent_app_type] => utility
[patent_app_number] => 12/945122
[patent_app_country] => US
[patent_app_date] => 2010-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 4394
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12945122
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/945122 | Method for producing layout of semiconductor integrated circuit with radio frequency devices | Nov 11, 2010 | Issued |
Array
(
[id] => 8189462
[patent_doc_number] => 20120117524
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-05-10
[patent_title] => 'REUSABLE STRUCTURED HARDWARE DESCRIPTION LANGUAGE DESIGN COMPONENT'
[patent_app_type] => utility
[patent_app_number] => 12/940762
[patent_app_country] => US
[patent_app_date] => 2010-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6779
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0117/20120117524.pdf
[firstpage_image] =>[orig_patent_app_number] => 12940762
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/940762 | Reusable structured hardware description language design component | Nov 4, 2010 | Issued |
Array
(
[id] => 8235666
[patent_doc_number] => 08201130
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2012-06-12
[patent_title] => 'Parallel signal routing'
[patent_app_type] => utility
[patent_app_number] => 12/939732
[patent_app_country] => US
[patent_app_date] => 2010-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 6459
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 213
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/201/08201130.pdf
[firstpage_image] =>[orig_patent_app_number] => 12939732
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/939732 | Parallel signal routing | Nov 3, 2010 | Issued |
Array
(
[id] => 7563094
[patent_doc_number] => 20110276928
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-11-10
[patent_title] => 'METHOD FOR CONTROLLING PATTERN UNIFORMITY OF SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/915570
[patent_app_country] => US
[patent_app_date] => 2010-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3158
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0276/20110276928.pdf
[firstpage_image] =>[orig_patent_app_number] => 12915570
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/915570 | Method for controlling pattern uniformity of semiconductor device | Oct 28, 2010 | Issued |
Array
(
[id] => 8355157
[patent_doc_number] => 08250507
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2012-08-21
[patent_title] => 'Distributing computations in a parallel processing environment'
[patent_app_type] => utility
[patent_app_number] => 12/909521
[patent_app_country] => US
[patent_app_date] => 2010-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 9862
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12909521
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/909521 | Distributing computations in a parallel processing environment | Oct 20, 2010 | Issued |
Array
(
[id] => 10873393
[patent_doc_number] => 08898611
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-11-25
[patent_title] => 'VLSI layouts of fully connected generalized and pyramid networks with locality exploitation'
[patent_app_type] => utility
[patent_app_number] => 13/502207
[patent_app_country] => US
[patent_app_date] => 2010-10-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 43
[patent_figures_cnt] => 51
[patent_no_of_words] => 47603
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 518
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13502207
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/502207 | VLSI layouts of fully connected generalized and pyramid networks with locality exploitation | Oct 15, 2010 | Issued |
Array
(
[id] => 6121693
[patent_doc_number] => 20110084744
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-04-14
[patent_title] => 'Semiconductor device, adjustment method thereof and data processing system'
[patent_app_type] => utility
[patent_app_number] => 12/923792
[patent_app_country] => US
[patent_app_date] => 2010-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 17848
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0084/20110084744.pdf
[firstpage_image] =>[orig_patent_app_number] => 12923792
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/923792 | Semiconductor device, adjustment method thereof and data processing system | Oct 6, 2010 | Issued |
Array
(
[id] => 8098275
[patent_doc_number] => 20120084743
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-04-05
[patent_title] => 'METHOD AND APPARATUS FOR IMPROVING THE INTERCONNECTION AND MULTIPLEXING COST OF CIRCUIT DESIGN FROM HIGH LEVEL SYNTHESIS USING ANT COLONY OPTIMIZATION'
[patent_app_type] => utility
[patent_app_number] => 12/894842
[patent_app_country] => US
[patent_app_date] => 2010-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 12698
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0084/20120084743.pdf
[firstpage_image] =>[orig_patent_app_number] => 12894842
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/894842 | Method and apparatus for improving the interconnection and multiplexing cost of circuit design from high level synthesis using ant colony optimization | Sep 29, 2010 | Issued |
Array
(
[id] => 8098271
[patent_doc_number] => 20120084742
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-04-05
[patent_title] => 'METHOD AND APPARATUS FOR USING ENTROPY IN ANT COLONY OPTIMIZATION CIRCUIT DESIGN FROM HIGH LEVEL SYNTHESIS'
[patent_app_type] => utility
[patent_app_number] => 12/894756
[patent_app_country] => US
[patent_app_date] => 2010-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 12672
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0084/20120084742.pdf
[firstpage_image] =>[orig_patent_app_number] => 12894756
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/894756 | Method and apparatus for using entropy in ant colony optimization circuit design from high level synthesis | Sep 29, 2010 | Issued |
Array
(
[id] => 8096919
[patent_doc_number] => 20120084067
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-04-05
[patent_title] => 'METHOD AND APPARATUS FOR SYNTHESIZING PIPELINED INPUT/OUTPUT IN A CIRCUIT DESIGN FROM HIGH LEVEL SYNTHESIS'
[patent_app_type] => utility
[patent_app_number] => 12/894902
[patent_app_country] => US
[patent_app_date] => 2010-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 12717
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0084/20120084067.pdf
[firstpage_image] =>[orig_patent_app_number] => 12894902
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/894902 | Method and apparatus for synthesizing pipelined input/output in a circuit design from high level synthesis | Sep 29, 2010 | Issued |
Array
(
[id] => 8985293
[patent_doc_number] => 08516423
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-08-20
[patent_title] => 'System and method for determining simulated response extrema for integrated circuit power supply networks'
[patent_app_type] => utility
[patent_app_number] => 12/894102
[patent_app_country] => US
[patent_app_date] => 2010-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 22
[patent_no_of_words] => 16741
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12894102
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/894102 | System and method for determining simulated response extrema for integrated circuit power supply networks | Sep 28, 2010 | Issued |
Array
(
[id] => 6146705
[patent_doc_number] => 20110018879
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-01-27
[patent_title] => 'Pattern generation method and pattern generation program'
[patent_app_type] => utility
[patent_app_number] => 12/923512
[patent_app_country] => US
[patent_app_date] => 2010-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5148
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0018/20110018879.pdf
[firstpage_image] =>[orig_patent_app_number] => 12923512
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/923512 | Pattern generation method and pattern generation program | Sep 23, 2010 | Issued |