Suchin Parihar

Array ( [id] => 8022969 [patent_doc_number] => 08141004 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-03-20 [patent_title] => 'Solution-dependent regularization method for quantizing continuous-tone lithography masks' [patent_app_type] => utility [patent_app_number] => 12/777940 [patent_app_country] => US [patent_app_date] => 2010-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6035 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/141/08141004.pdf [firstpage_image] =>[orig_patent_app_number] => 12777940 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7563097 [patent_doc_number] => 20110276931 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-10 [patent_title] => 'Eliminating, Coalescing, or Bypassing Ports in Memory Array Representations' [patent_app_type] => utility [patent_app_number] => 12/775622 [patent_app_country] => US [patent_app_date] => 2010-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 10582 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0276/20110276931.pdf [firstpage_image] =>[orig_patent_app_number] => 12775622 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7504016 [patent_doc_number] => 20110265051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-27 [patent_title] => 'Method for Substrate Noise Analysis' [patent_app_type] => utility [patent_app_number] => 12/766732 [patent_app_country] => US [patent_app_date] => 2010-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6182 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20110265051.pdf [firstpage_image] =>[orig_patent_app_number] => 12766732 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8741300 [patent_doc_number] => 08413087 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-04-02 [patent_title] => 'Method and mechanism for implementing region query using hierarchical grids' [patent_app_type] => utility [patent_app_number] => 12/748172 [patent_app_country] => US [patent_app_date] => 2010-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 15575 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12748172 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6009004 [patent_doc_number] => 20110061036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-10 [patent_title] => 'TIMING LIBRARY TEST APPARATUS, METHOD FOR TESTING TIMING LIBRARY, AND COMPUTER READABLE MEDIUM COMPRISING TIMING LIBRARY TEST PROGRAM' [patent_app_type] => utility [patent_app_number] => 12/729632 [patent_app_country] => US [patent_app_date] => 2010-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4933 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20110061036.pdf [firstpage_image] =>[orig_patent_app_number] => 12729632 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6286226 [patent_doc_number] => 20100237469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-23 [patent_title] => 'PHOTOMASK, SEMICONDUCTOR DEVICE, AND CHARGED BEAM WRITING APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/726052 [patent_app_country] => US [patent_app_date] => 2010-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4173 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20100237469.pdf [firstpage_image] =>[orig_patent_app_number] => 12726052 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6286381 [patent_doc_number] => 20100237540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-23 [patent_title] => 'METHOD OF DESIGNING A TEMPLATE PATTERN, METHOD OF MANUFACTURING A TEMPLATE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/725202 [patent_app_country] => US [patent_app_date] => 2010-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4535 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20100237540.pdf [firstpage_image] =>[orig_patent_app_number] => 12725202 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9062996 [patent_doc_number] => 08549451 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-01 [patent_title] => 'Verification apparatus' [patent_app_type] => utility [patent_app_number] => 12/715562 [patent_app_country] => US [patent_app_date] => 2010-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 42 [patent_no_of_words] => 6406 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12715562 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8022991 [patent_doc_number] => 08141015 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-03-20 [patent_title] => 'Reporting status of timing exceptions' [patent_app_type] => utility [patent_app_number] => 12/716234 [patent_app_country] => US [patent_app_date] => 2010-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6839 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/141/08141015.pdf [firstpage_image] =>[orig_patent_app_number] => 12716234 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8285834 [patent_doc_number] => 08219951 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-10 [patent_title] => 'Method of thermal density optimization for device and process enhancement' [patent_app_type] => utility [patent_app_number] => 12/713902 [patent_app_country] => US [patent_app_date] => 2010-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 7976 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12713902 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8763395 [patent_doc_number] => 08423934 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-04-16 [patent_title] => 'Model validation cockpit' [patent_app_type] => utility [patent_app_number] => 12/710212 [patent_app_country] => US [patent_app_date] => 2010-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 5321 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12710212 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9218556 [patent_doc_number] => 08631366 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-14 [patent_title] => 'Integrated circuit design using DFM-enhanced architecture' [patent_app_type] => utility [patent_app_number] => 12/708242 [patent_app_country] => US [patent_app_date] => 2010-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3870 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12708242 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8285842 [patent_doc_number] => 08219957 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-07-10 [patent_title] => 'Global placement legalization for complex packing rules' [patent_app_type] => utility [patent_app_number] => 12/698902 [patent_app_country] => US [patent_app_date] => 2010-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 7612 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12698902 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8561943 [patent_doc_number] => 08336015 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-18 [patent_title] => 'Pre-route and post-route net correlation with defined patterns' [patent_app_type] => utility [patent_app_number] => 12/697142 [patent_app_country] => US [patent_app_date] => 2010-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5584 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12697142 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9358747 [patent_doc_number] => 08677302 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-18 [patent_title] => 'Multi-threaded detailed routing' [patent_app_type] => utility [patent_app_number] => 12/695452 [patent_app_country] => US [patent_app_date] => 2010-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 8339 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12695452 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8267594 [patent_doc_number] => 20120167020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-28 [patent_title] => 'Pre-OPC Layout Editing For Improved Image Fidelity' [patent_app_type] => utility [patent_app_number] => 13/145992 [patent_app_country] => US [patent_app_date] => 2010-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9704 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13145992 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8703958 [patent_doc_number] => 08397195 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-12 [patent_title] => 'Method and system for packet switch based logic replication' [patent_app_type] => utility [patent_app_number] => 12/692562 [patent_app_country] => US [patent_app_date] => 2010-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10910 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12692562 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6566161 [patent_doc_number] => 20100223590 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-02 [patent_title] => 'Mask Decomposition for Double Dipole Lithography' [patent_app_type] => utility [patent_app_number] => 12/689972 [patent_app_country] => US [patent_app_date] => 2010-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6206 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0223/20100223590.pdf [firstpage_image] =>[orig_patent_app_number] => 12689972 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6191295 [patent_doc_number] => 20110173579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-14 [patent_title] => 'Rectilinear Covering Method With Bounded Number of Rectangles for Designing a VLSI Chip' [patent_app_type] => utility [patent_app_number] => 12/686412 [patent_app_country] => US [patent_app_date] => 2010-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5631 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20110173579.pdf [firstpage_image] =>[orig_patent_app_number] => 12686412 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8633030 [patent_doc_number] => 08365129 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-29 [patent_title] => 'Edge routing using connection regions' [patent_app_type] => utility [patent_app_number] => 12/631102 [patent_app_country] => US [patent_app_date] => 2009-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4902 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12631102 [rel_patent_id] =>[rel_patent_doc_number] =>)