Search

Suchin Parihar

Examiner (ID: 4481, Phone: (571)272-6210 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851, 2872
Total Applications
1385
Issued Applications
1167
Pending Applications
109
Abandoned Applications
148

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8530731 [patent_doc_number] => 08307315 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-06 [patent_title] => 'Methods and apparatuses for circuit design and optimization' [patent_app_type] => utility [patent_app_number] => 12/363212 [patent_app_country] => US [patent_app_date] => 2009-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 24 [patent_no_of_words] => 9352 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12363212 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/363212
Methods and apparatuses for circuit design and optimization Jan 29, 2009 Issued
Array ( [id] => 7813516 [patent_doc_number] => 08136054 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-13 [patent_title] => 'Compact abbe\'s kernel generation using principal component analysis' [patent_app_type] => utility [patent_app_number] => 12/362311 [patent_app_country] => US [patent_app_date] => 2009-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5591 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/136/08136054.pdf [firstpage_image] =>[orig_patent_app_number] => 12362311 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/362311
Compact abbe's kernel generation using principal component analysis Jan 28, 2009 Issued
Array ( [id] => 8033883 [patent_doc_number] => 08146036 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-03-27 [patent_title] => 'Circuit for and method of determining a process corner for a CMOS device' [patent_app_type] => utility [patent_app_number] => 12/361722 [patent_app_country] => US [patent_app_date] => 2009-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 5379 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/146/08146036.pdf [firstpage_image] =>[orig_patent_app_number] => 12361722 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/361722
Circuit for and method of determining a process corner for a CMOS device Jan 28, 2009 Issued
Array ( [id] => 6480752 [patent_doc_number] => 20100192111 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-29 [patent_title] => 'PERFORMING LOGIC OPTIMIZATION AND STATE-SPACE REDUCTION FOR HYBRID VERIFICATION' [patent_app_type] => utility [patent_app_number] => 12/361282 [patent_app_country] => US [patent_app_date] => 2009-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7223 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0192/20100192111.pdf [firstpage_image] =>[orig_patent_app_number] => 12361282 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/361282
Performing logic optimization and state-space reduction for hybrid verification Jan 27, 2009 Issued
Array ( [id] => 8389158 [patent_doc_number] => 08266568 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-11 [patent_title] => 'Power mesh management method' [patent_app_type] => utility [patent_app_number] => 12/359911 [patent_app_country] => US [patent_app_date] => 2009-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3899 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12359911 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/359911
Power mesh management method Jan 25, 2009 Issued
Array ( [id] => 5381531 [patent_doc_number] => 20090193370 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-30 [patent_title] => ' Bondwire Design' [patent_app_type] => utility [patent_app_number] => 12/359131 [patent_app_country] => US [patent_app_date] => 2009-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6349 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20090193370.pdf [firstpage_image] =>[orig_patent_app_number] => 12359131 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/359131
Bondwire design Jan 22, 2009 Issued
Array ( [id] => 6460890 [patent_doc_number] => 20100190277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-29 [patent_title] => 'Power Network Stacked Via Removal For Congestion Reduction' [patent_app_type] => utility [patent_app_number] => 12/359091 [patent_app_country] => US [patent_app_date] => 2009-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6495 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20100190277.pdf [firstpage_image] =>[orig_patent_app_number] => 12359091 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/359091
Power network stacked via removal for congestion reduction Jan 22, 2009 Issued
Array ( [id] => 6234635 [patent_doc_number] => 20100185998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-22 [patent_title] => 'METHOD FOR OPC CORRECTION' [patent_app_type] => utility [patent_app_number] => 12/356482 [patent_app_country] => US [patent_app_date] => 2009-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1953 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20100185998.pdf [firstpage_image] =>[orig_patent_app_number] => 12356482 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/356482
Method for OPC correction Jan 19, 2009 Issued
Array ( [id] => 6405637 [patent_doc_number] => 20100179679 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-15 [patent_title] => 'Generating Cutting Forms Along Current Flow Direction In A Circuit Layout' [patent_app_type] => utility [patent_app_number] => 12/352782 [patent_app_country] => US [patent_app_date] => 2009-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4518 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20100179679.pdf [firstpage_image] =>[orig_patent_app_number] => 12352782 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/352782
Generating cutting forms along current flow direction in a circuit layout Jan 12, 2009 Issued
Array ( [id] => 5381545 [patent_doc_number] => 20090193384 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-30 [patent_title] => 'SHIFT-ENABLED RECONFIGURABLE DEVICE' [patent_app_type] => utility [patent_app_number] => 12/352562 [patent_app_country] => US [patent_app_date] => 2009-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4255 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20090193384.pdf [firstpage_image] =>[orig_patent_app_number] => 12352562 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/352562
SHIFT-ENABLED RECONFIGURABLE DEVICE Jan 11, 2009 Abandoned
Array ( [id] => 6647206 [patent_doc_number] => 20100174957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-08 [patent_title] => 'CORRELATION AND OVERLAY OF LARGE DESIGN PHYSICAL PARTITIONS AND EMBEDDED MACROS TO DETECT IN-LINE DEFECTS' [patent_app_type] => utility [patent_app_number] => 12/350261 [patent_app_country] => US [patent_app_date] => 2009-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2692 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20100174957.pdf [firstpage_image] =>[orig_patent_app_number] => 12350261 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/350261
CORRELATION AND OVERLAY OF LARGE DESIGN PHYSICAL PARTITIONS AND EMBEDDED MACROS TO DETECT IN-LINE DEFECTS Jan 7, 2009 Abandoned
Array ( [id] => 7726404 [patent_doc_number] => 08099684 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-17 [patent_title] => 'Methodology of placing printing assist feature for random mask layout' [patent_app_type] => utility [patent_app_number] => 12/350251 [patent_app_country] => US [patent_app_date] => 2009-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6571 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/099/08099684.pdf [firstpage_image] =>[orig_patent_app_number] => 12350251 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/350251
Methodology of placing printing assist feature for random mask layout Jan 7, 2009 Issued
Array ( [id] => 5438025 [patent_doc_number] => 20090172612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'STATIC HAZARD DETECTION DEVICE, STATIC HAZARD DETECTION METHOD, AND RECORDING MEDIUM' [patent_app_type] => utility [patent_app_number] => 12/343212 [patent_app_country] => US [patent_app_date] => 2008-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 12357 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20090172612.pdf [firstpage_image] =>[orig_patent_app_number] => 12343212 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/343212
Static hazard detection device, static hazard detection method, and recording medium Dec 22, 2008 Issued
Array ( [id] => 5503493 [patent_doc_number] => 20090164181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-25 [patent_title] => 'Apparatus and Method for Modeling MOS Transistor' [patent_app_type] => utility [patent_app_number] => 12/341612 [patent_app_country] => US [patent_app_date] => 2008-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2607 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20090164181.pdf [firstpage_image] =>[orig_patent_app_number] => 12341612 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/341612
Apparatus and Method for Modeling MOS Transistor Dec 21, 2008 Abandoned
Array ( [id] => 8752248 [patent_doc_number] => 08418092 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-09 [patent_title] => 'Source-synchronous data link for system-on-chip design' [patent_app_type] => utility [patent_app_number] => 12/746302 [patent_app_country] => US [patent_app_date] => 2008-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4379 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12746302 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/746302
Source-synchronous data link for system-on-chip design Nov 26, 2008 Issued
Array ( [id] => 6630245 [patent_doc_number] => 20100100859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-22 [patent_title] => 'DESIGN METHODOLOGY FOR PREVENTING FUNCTIONAL FAILURE CAUSED BY CDM ESD' [patent_app_type] => utility [patent_app_number] => 12/255002 [patent_app_country] => US [patent_app_date] => 2008-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1504 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0100/20100100859.pdf [firstpage_image] =>[orig_patent_app_number] => 12255002 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/255002
Methodology for preventing functional failure caused by CDM ESD Oct 20, 2008 Issued
Array ( [id] => 7734826 [patent_doc_number] => 08103979 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-24 [patent_title] => 'System for generating and optimizing mask assist features based on hybrid (model and rules) methodology' [patent_app_type] => utility [patent_app_number] => 12/254172 [patent_app_country] => US [patent_app_date] => 2008-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 2882 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/103/08103979.pdf [firstpage_image] =>[orig_patent_app_number] => 12254172 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/254172
System for generating and optimizing mask assist features based on hybrid (model and rules) methodology Oct 19, 2008 Issued
Array ( [id] => 7525090 [patent_doc_number] => 08028260 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-09-27 [patent_title] => 'Determination of most critical timing paths in digital circuits' [patent_app_type] => utility [patent_app_number] => 12/251002 [patent_app_country] => US [patent_app_date] => 2008-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7765 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/028/08028260.pdf [firstpage_image] =>[orig_patent_app_number] => 12251002 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/251002
Determination of most critical timing paths in digital circuits Oct 13, 2008 Issued
Array ( [id] => 5535425 [patent_doc_number] => 20090235213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-17 [patent_title] => 'Layout-Versus-Schematic Analysis For Symmetric Circuits' [patent_app_type] => utility [patent_app_number] => 12/248032 [patent_app_country] => US [patent_app_date] => 2008-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6594 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20090235213.pdf [firstpage_image] =>[orig_patent_app_number] => 12248032 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/248032
Layout-Versus-Schematic Analysis For Symmetric Circuits Oct 7, 2008 Abandoned
Array ( [id] => 6369656 [patent_doc_number] => 20100088658 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-08 [patent_title] => 'METHOD AND APPARATUS FOR EFFICIENT INCREMENTAL STATISTICAL TIMING ANALYSIS AND OPTIMIZATION' [patent_app_type] => utility [patent_app_number] => 12/244512 [patent_app_country] => US [patent_app_date] => 2008-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4180 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20100088658.pdf [firstpage_image] =>[orig_patent_app_number] => 12244512 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/244512
Method and apparatus for efficient incremental statistical timing analysis and optimization Oct 1, 2008 Issued
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