Search

Suchin Parihar

Examiner (ID: 4041, Phone: (571)272-6210 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851, 2872
Total Applications
1418
Issued Applications
1198
Pending Applications
84
Abandoned Applications
154

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8022991 [patent_doc_number] => 08141015 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-03-20 [patent_title] => 'Reporting status of timing exceptions' [patent_app_type] => utility [patent_app_number] => 12/716234 [patent_app_country] => US [patent_app_date] => 2010-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6839 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/141/08141015.pdf [firstpage_image] =>[orig_patent_app_number] => 12716234 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/716234
Reporting status of timing exceptions Mar 1, 2010 Issued
Array ( [id] => 9062996 [patent_doc_number] => 08549451 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-01 [patent_title] => 'Verification apparatus' [patent_app_type] => utility [patent_app_number] => 12/715562 [patent_app_country] => US [patent_app_date] => 2010-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 42 [patent_no_of_words] => 6406 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12715562 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/715562
Verification apparatus Mar 1, 2010 Issued
Array ( [id] => 8285834 [patent_doc_number] => 08219951 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-10 [patent_title] => 'Method of thermal density optimization for device and process enhancement' [patent_app_type] => utility [patent_app_number] => 12/713902 [patent_app_country] => US [patent_app_date] => 2010-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 7976 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12713902 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/713902
Method of thermal density optimization for device and process enhancement Feb 25, 2010 Issued
Array ( [id] => 8763395 [patent_doc_number] => 08423934 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-04-16 [patent_title] => 'Model validation cockpit' [patent_app_type] => utility [patent_app_number] => 12/710212 [patent_app_country] => US [patent_app_date] => 2010-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 5321 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12710212 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/710212
Model validation cockpit Feb 21, 2010 Issued
Array ( [id] => 9218556 [patent_doc_number] => 08631366 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-14 [patent_title] => 'Integrated circuit design using DFM-enhanced architecture' [patent_app_type] => utility [patent_app_number] => 12/708242 [patent_app_country] => US [patent_app_date] => 2010-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3870 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12708242 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/708242
Integrated circuit design using DFM-enhanced architecture Feb 17, 2010 Issued
Array ( [id] => 8285842 [patent_doc_number] => 08219957 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-07-10 [patent_title] => 'Global placement legalization for complex packing rules' [patent_app_type] => utility [patent_app_number] => 12/698902 [patent_app_country] => US [patent_app_date] => 2010-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 7612 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12698902 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/698902
Global placement legalization for complex packing rules Feb 1, 2010 Issued
Array ( [id] => 8561943 [patent_doc_number] => 08336015 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-18 [patent_title] => 'Pre-route and post-route net correlation with defined patterns' [patent_app_type] => utility [patent_app_number] => 12/697142 [patent_app_country] => US [patent_app_date] => 2010-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5584 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12697142 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/697142
Pre-route and post-route net correlation with defined patterns Jan 28, 2010 Issued
Array ( [id] => 9358747 [patent_doc_number] => 08677302 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-18 [patent_title] => 'Multi-threaded detailed routing' [patent_app_type] => utility [patent_app_number] => 12/695452 [patent_app_country] => US [patent_app_date] => 2010-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 8339 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12695452 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/695452
Multi-threaded detailed routing Jan 27, 2010 Issued
Array ( [id] => 8267594 [patent_doc_number] => 20120167020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-28 [patent_title] => 'Pre-OPC Layout Editing For Improved Image Fidelity' [patent_app_type] => utility [patent_app_number] => 13/145992 [patent_app_country] => US [patent_app_date] => 2010-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9704 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13145992 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/145992
Pre-OPC Layout Editing For Improved Image Fidelity Jan 21, 2010 Abandoned
Array ( [id] => 8703958 [patent_doc_number] => 08397195 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-12 [patent_title] => 'Method and system for packet switch based logic replication' [patent_app_type] => utility [patent_app_number] => 12/692562 [patent_app_country] => US [patent_app_date] => 2010-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10910 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12692562 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/692562
Method and system for packet switch based logic replication Jan 21, 2010 Issued
Array ( [id] => 6566161 [patent_doc_number] => 20100223590 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-02 [patent_title] => 'Mask Decomposition for Double Dipole Lithography' [patent_app_type] => utility [patent_app_number] => 12/689972 [patent_app_country] => US [patent_app_date] => 2010-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6206 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0223/20100223590.pdf [firstpage_image] =>[orig_patent_app_number] => 12689972 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/689972
Mask decomposition for double dipole lithography Jan 18, 2010 Issued
Array ( [id] => 6191295 [patent_doc_number] => 20110173579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-14 [patent_title] => 'Rectilinear Covering Method With Bounded Number of Rectangles for Designing a VLSI Chip' [patent_app_type] => utility [patent_app_number] => 12/686412 [patent_app_country] => US [patent_app_date] => 2010-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5631 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20110173579.pdf [firstpage_image] =>[orig_patent_app_number] => 12686412 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/686412
Rectilinear covering method with bounded number of rectangles for designing a VLSI chip Jan 12, 2010 Issued
Array ( [id] => 8633030 [patent_doc_number] => 08365129 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-29 [patent_title] => 'Edge routing using connection regions' [patent_app_type] => utility [patent_app_number] => 12/631102 [patent_app_country] => US [patent_app_date] => 2009-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4902 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12631102 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/631102
Edge routing using connection regions Dec 3, 2009 Issued
Array ( [id] => 5940338 [patent_doc_number] => 20110214103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-01 [patent_title] => 'ELECTRICAL CIRCUIT ARRANGEMENT AND METHOD FOR DESIGNING AN ELECTRICAL CIRCUIT ARRANGEMENT' [patent_app_type] => utility [patent_app_number] => 13/127122 [patent_app_country] => US [patent_app_date] => 2009-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7920 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0214/20110214103.pdf [firstpage_image] =>[orig_patent_app_number] => 13127122 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/127122
ELECTRICAL CIRCUIT ARRANGEMENT AND METHOD FOR DESIGNING AN ELECTRICAL CIRCUIT ARRANGEMENT Nov 4, 2009 Abandoned
Array ( [id] => 8449286 [patent_doc_number] => 08291356 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-16 [patent_title] => 'Methods and apparatuses for automated circuit design' [patent_app_type] => utility [patent_app_number] => 12/580796 [patent_app_country] => US [patent_app_date] => 2009-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8262 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12580796 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/580796
Methods and apparatuses for automated circuit design Oct 15, 2009 Issued
Array ( [id] => 8971861 [patent_doc_number] => 08510691 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-13 [patent_title] => 'Semiconductor verification apparatus, method and program' [patent_app_type] => utility [patent_app_number] => 13/120622 [patent_app_country] => US [patent_app_date] => 2009-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 11260 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13120622 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/120622
Semiconductor verification apparatus, method and program Oct 7, 2009 Issued
Array ( [id] => 9404881 [patent_doc_number] => 08694946 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-04-08 [patent_title] => 'Simultaneous switching noise optimization' [patent_app_type] => utility [patent_app_number] => 12/465452 [patent_app_country] => US [patent_app_date] => 2009-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5633 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12465452 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/465452
Simultaneous switching noise optimization May 12, 2009 Issued
Array ( [id] => 6464879 [patent_doc_number] => 20100281442 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-04 [patent_title] => 'TECHNIQUE FOR DETERMINING CIRCUIT INTERDEPENDENCIES' [patent_app_type] => utility [patent_app_number] => 12/432002 [patent_app_country] => US [patent_app_date] => 2009-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5286 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0281/20100281442.pdf [firstpage_image] =>[orig_patent_app_number] => 12432002 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/432002
Technique for determining circuit interdependencies Apr 28, 2009 Issued
Array ( [id] => 7726410 [patent_doc_number] => 08099690 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-17 [patent_title] => 'Adaptive state-to-symbolic transformation in a canonical representation' [patent_app_type] => utility [patent_app_number] => 12/430322 [patent_app_country] => US [patent_app_date] => 2009-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6694 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/099/08099690.pdf [firstpage_image] =>[orig_patent_app_number] => 12430322 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/430322
Adaptive state-to-symbolic transformation in a canonical representation Apr 26, 2009 Issued
Array ( [id] => 7813535 [patent_doc_number] => 08136073 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-03-13 [patent_title] => 'Circuit design fitting' [patent_app_type] => utility [patent_app_number] => 12/429842 [patent_app_country] => US [patent_app_date] => 2009-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10369 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/136/08136073.pdf [firstpage_image] =>[orig_patent_app_number] => 12429842 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/429842
Circuit design fitting Apr 23, 2009 Issued
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